/*
 * Copyright 2022 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */


#ifndef _dpcs_4_2_3_SH_MASK_HEADER
#define _dpcs_4_2_3_SH_MASK_HEADER


// addressBlock: dpcssys_dpcssys_cr0_dispdec
//DPCSSYS_CR0_DPCSSYS_CR_ADDR
#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
#define DPCSSYS_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
//DPCSSYS_CR0_DPCSSYS_CR_DATA
#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
#define DPCSSYS_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL


// addressBlock: dpcssys_dpcssys_cr1_dispdec
//DPCSSYS_CR1_DPCSSYS_CR_ADDR
#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
#define DPCSSYS_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
//DPCSSYS_CR1_DPCSSYS_CR_DATA
#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
#define DPCSSYS_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL


// addressBlock: dpcssys_dpcssys_cr2_dispdec
//DPCSSYS_CR2_DPCSSYS_CR_ADDR
#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
#define DPCSSYS_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
//DPCSSYS_CR2_DPCSSYS_CR_DATA
#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
#define DPCSSYS_CR2_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL


// addressBlock: dpcssys_dpcssys_cr3_dispdec
//DPCSSYS_CR3_DPCSSYS_CR_ADDR
#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
#define DPCSSYS_CR3_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
//DPCSSYS_CR3_DPCSSYS_CR_DATA
#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
#define DPCSSYS_CR3_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL


// addressBlock: dpcssys_dpcssys_cr4_dispdec
//DPCSSYS_CR4_DPCSSYS_CR_ADDR
#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                  0x0
#define DPCSSYS_CR4_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                    0x0000FFFFL
//DPCSSYS_CR4_DPCSSYS_CR_DATA
#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                  0x0
#define DPCSSYS_CR4_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                    0x0000FFFFL


// addressBlock: dpcssys_pwrseq0_dispdec_pwrseq_dispdec
//PWRSEQ0_DC_GPIO_PWRSEQ_EN
#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
#define PWRSEQ0_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
//PWRSEQ0_DC_GPIO_PWRSEQ_CTRL
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
#define PWRSEQ0_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
//PWRSEQ0_DC_GPIO_PWRSEQ_MASK
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
#define PWRSEQ0_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
//PWRSEQ0_DC_GPIO_PWRSEQ_A_Y
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
#define PWRSEQ0_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
//PWRSEQ0_PANEL_PWRSEQ_CNTL
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
#define PWRSEQ0_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
//PWRSEQ0_PANEL_PWRSEQ_STATE
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
#define PWRSEQ0_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
//PWRSEQ0_PANEL_PWRSEQ_DELAY1
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
#define PWRSEQ0_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
//PWRSEQ0_PANEL_PWRSEQ_DELAY2
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
#define PWRSEQ0_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
//PWRSEQ0_PANEL_PWRSEQ_REF_DIV1
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
//PWRSEQ0_BL_PWM_CNTL
#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
#define PWRSEQ0_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
#define PWRSEQ0_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
#define PWRSEQ0_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
#define PWRSEQ0_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
//PWRSEQ0_BL_PWM_CNTL2
#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
#define PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                           0x1c
#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
#define PWRSEQ0_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                             0x30000000L
#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
#define PWRSEQ0_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
//PWRSEQ0_BL_PWM_PERIOD_CNTL
#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
#define PWRSEQ0_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
//PWRSEQ0_BL_PWM_GRP1_REG_LOCK
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
#define PWRSEQ0_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
//PWRSEQ0_PANEL_PWRSEQ_REF_DIV2
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
#define PWRSEQ0_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
//PWRSEQ0_PWRSEQ_SPARE
#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
#define PWRSEQ0_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL


// addressBlock: dpcssys_pwrseq1_dispdec_pwrseq_dispdec
//PWRSEQ1_DC_GPIO_PWRSEQ_EN
#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN__SHIFT                                                  0x0
#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT                                                    0x8
#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT                                                     0x10
#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_EN_MASK                                                    0x00000001L
#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK                                                      0x00000100L
#define PWRSEQ1_DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK                                                       0x00010000L
//PWRSEQ1_DC_GPIO_PWRSEQ_CTRL
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN__SHIFT                                           0x0
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN__SHIFT                                             0x1
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN__SHIFT                                              0x2
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN__SHIFT                                              0x3
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN__SHIFT                                                0x4
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN__SHIFT                                                 0x5
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN__SHIFT                                             0x6
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN__SHIFT                                               0x7
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN__SHIFT                                                0x8
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN__SHIFT                                                0x10
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP__SHIFT                                                0x14
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_TX12_EN_MASK                                             0x00000001L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_TX12_EN_MASK                                               0x00000002L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_TX12_EN_MASK                                                0x00000004L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_RXEN_MASK                                                0x00000008L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_RXEN_MASK                                                  0x00000010L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_RXEN_MASK                                                   0x00000020L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_VARY_BL_PU_EN_MASK                                               0x00000040L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_DIGON_PU_EN_MASK                                                 0x00000080L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__DC_GPIO_BLON_PU_EN_MASK                                                  0x00000100L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SN_MASK                                                  0x000F0000L
#define PWRSEQ1_DC_GPIO_PWRSEQ_CTRL__PWRSEQ_STRENGTH_SP_MASK                                                  0x00F00000L
//PWRSEQ1_DC_GPIO_PWRSEQ_MASK
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK__SHIFT                                              0x0
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS__SHIFT                                            0x4
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV__SHIFT                                              0x6
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT                                                0x8
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT                                              0xc
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT                                                0xe
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT                                                 0x10
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT                                               0x14
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT                                                 0x16
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_MASK_MASK                                                0x00000001L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_PD_DIS_MASK                                              0x00000010L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_VARY_BL_RECV_MASK                                                0x000000C0L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK                                                  0x00000100L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK                                                0x00001000L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK                                                  0x0000C000L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK                                                   0x00010000L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK                                                 0x00100000L
#define PWRSEQ1_DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK                                                   0x00C00000L
//PWRSEQ1_DC_GPIO_PWRSEQ_A_Y
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A__SHIFT                                                  0x0
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y__SHIFT                                                  0x1
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A__SHIFT                                                    0x8
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y__SHIFT                                                    0x9
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A__SHIFT                                                     0x10
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y__SHIFT                                                     0x11
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_A_MASK                                                    0x00000001L
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_VARY_BL_Y_MASK                                                    0x00000002L
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_A_MASK                                                      0x00000100L
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_DIGON_Y_MASK                                                      0x00000200L
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_A_MASK                                                       0x00010000L
#define PWRSEQ1_DC_GPIO_PWRSEQ_A_Y__DC_GPIO_BLON_Y_MASK                                                       0x00020000L
//PWRSEQ1_PANEL_PWRSEQ_CNTL
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN__SHIFT                                                     0x0
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE__SHIFT                                           0x4
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN__SHIFT                                                        0x8
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD__SHIFT                                                   0x9
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL__SHIFT                                                    0xa
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON__SHIFT                                                         0x10
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD__SHIFT                                                    0x11
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL__SHIFT                                                     0x12
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON__SHIFT                                                          0x18
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD__SHIFT                                                     0x19
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL__SHIFT                                                      0x1a
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_EN_MASK                                                       0x00000001L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_PWRSEQ_TARGET_STATE_MASK                                             0x00000010L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_MASK                                                          0x00000100L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_OVRD_MASK                                                     0x00000200L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_SYNCEN_POL_MASK                                                      0x00000400L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_MASK                                                           0x00010000L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_OVRD_MASK                                                      0x00020000L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_DIGON_POL_MASK                                                       0x00040000L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_MASK                                                            0x01000000L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_OVRD_MASK                                                       0x02000000L
#define PWRSEQ1_PANEL_PWRSEQ_CNTL__PANEL_BLON_POL_MASK                                                        0x04000000L
//PWRSEQ1_PANEL_PWRSEQ_STATE
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R__SHIFT                                        0x0
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON__SHIFT                                                 0x1
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN__SHIFT                                                0x2
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON__SHIFT                                                  0x3
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE__SHIFT                                                  0x4
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE__SHIFT                                                 0x8
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_TARGET_STATE_R_MASK                                          0x00000001L
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DIGON_MASK                                                   0x00000002L
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_SYNCEN_MASK                                                  0x00000004L
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_BLON_MASK                                                    0x00000008L
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_DONE_MASK                                                    0x00000010L
#define PWRSEQ1_PANEL_PWRSEQ_STATE__PANEL_PWRSEQ_STATE_MASK                                                   0x00000F00L
//PWRSEQ1_PANEL_PWRSEQ_DELAY1
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1__SHIFT                                                0x0
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2__SHIFT                                                0x8
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1__SHIFT                                                0x10
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2__SHIFT                                                0x18
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY1_MASK                                                  0x000000FFL
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRUP_DELAY2_MASK                                                  0x0000FF00L
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY1_MASK                                                  0x00FF0000L
#define PWRSEQ1_PANEL_PWRSEQ_DELAY1__PANEL_PWRDN_DELAY2_MASK                                                  0xFF000000L
//PWRSEQ1_PANEL_PWRSEQ_DELAY2
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH__SHIFT                                            0x0
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3__SHIFT                                                0x8
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3__SHIFT                                                0x10
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN__SHIFT                                         0x18
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_MIN_LENGTH_MASK                                              0x000000FFL
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRUP_DELAY3_MASK                                                  0x0000FF00L
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_PWRDN_DELAY3_MASK                                                  0x00FF0000L
#define PWRSEQ1_PANEL_PWRSEQ_DELAY2__PANEL_VARY_BL_OVERRIDE_EN_MASK                                           0x01000000L
//PWRSEQ1_PANEL_PWRSEQ_REF_DIV1
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV__SHIFT                                            0x0
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV__SHIFT                                                  0x10
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__PANEL_PWRSEQ_REF_DIV_MASK                                              0x00000FFFL
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV1__BL_PWM_REF_DIV_MASK                                                    0xFFFF0000L
//PWRSEQ1_BL_PWM_CNTL
#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT                                                    0x0
#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO__SHIFT                                                         0x13
#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED__SHIFT                                              0x14
#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                            0x15
#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT                                                      0x1e
#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN__SHIFT                                                                 0x1f
#define PWRSEQ1_BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK                                                      0x0000FFFFL
#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_EQ_ZERO_MASK                                                           0x00080000L
#define PWRSEQ1_BL_PWM_CNTL__FRAME_START_EVENT_RECOGNIZED_MASK                                                0x00100000L
#define PWRSEQ1_BL_PWM_CNTL__RECOGNIZE_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                              0x00200000L
#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK                                                        0x40000000L
#define PWRSEQ1_BL_PWM_CNTL__BL_PWM_EN_MASK                                                                   0x80000000L
//PWRSEQ1_BL_PWM_CNTL2
#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT                              0x0
#define PWRSEQ1_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT                                           0x1c
#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT                                            0x1e
#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN__SHIFT                                          0x1f
#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK                                0x0000FFFFL
#define PWRSEQ1_BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK                                             0x30000000L
#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK                                              0x40000000L
#define PWRSEQ1_BL_PWM_CNTL2__BL_PWM_OVERRIDE_PANEL_PWRSEQ_EN_MASK                                            0x80000000L
//PWRSEQ1_BL_PWM_PERIOD_CNTL
#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT                                                      0x0
#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT                                               0x10
#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK                                                        0x0000FFFFL
#define PWRSEQ1_BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK                                                 0x000F0000L
//PWRSEQ1_BL_PWM_GRP1_REG_LOCK
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT                                             0x0
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT                                   0x8
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT                                0x10
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT                             0x18
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT                                0x1f
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK                                               0x00000001L
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK                                     0x00000100L
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK                                  0x00010000L
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK                               0x01000000L
#define PWRSEQ1_BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK                                  0x80000000L
//PWRSEQ1_PANEL_PWRSEQ_REF_DIV2
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV__SHIFT                                                    0x0
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV__SHIFT                                       0x8
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE__SHIFT                                0x10
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_DIV_MASK                                                      0x0000007FL
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__MICROSECOND_TIME_BASE_DIV_MASK                                         0x00007F00L
#define PWRSEQ1_PANEL_PWRSEQ_REF_DIV2__XTAL_REF_START_ON_VARY_BL_ACTIVE_MASK                                  0x00010000L
//PWRSEQ1_PWRSEQ_SPARE
#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE__SHIFT                                                             0x0
#define PWRSEQ1_PWRSEQ_SPARE__PWRSEQ_SPARE_MASK                                                               0xFFFFFFFFL


// addressBlock: dpcssys_dpcs0_rdpcstx0_dispdec
//RDPCSTX0_RDPCSTX_CNTL
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
#define RDPCSTX0_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
#define RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
//RDPCSTX0_RDPCSTX_CLOCK_CNTL
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
#define RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
//RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
#define RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA
#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
//RDPCSTX0_RDPCS_TX_CR_ADDR
#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
#define RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
//RDPCSTX0_RDPCS_TX_CR_DATA
#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
#define RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
//RDPCSTX0_RDPCS_TX_SRAM_CNTL
#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
#define RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
//RDPCSTX0_RDPCSTX_SCRATCH
#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
#define RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
//RDPCSTX0_RDPCSTX_SPARE
#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
#define RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
//RDPCSTX0_RDPCSTX_CNTL2
#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
#define RDPCSTX0_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
//RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
//RDPCSTX0_RDPCSTX_DEBUG_CONFIG
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL0
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL1
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
//RDPCSTX0_RDPCSTX_PHY_CNTL2
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
//RDPCSTX0_RDPCSTX_PHY_CNTL3
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL4
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL5
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL6
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
//RDPCSTX0_RDPCSTX_PHY_CNTL7
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
#define RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
//RDPCSTX0_RDPCSTX_PHY_CNTL8
#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
//RDPCSTX0_RDPCSTX_PHY_CNTL9
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
#define RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL10
#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
//RDPCSTX0_RDPCSTX_PHY_CNTL11
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL12
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
//RDPCSTX0_RDPCSTX_PHY_CNTL13
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL14
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
//RDPCSTX0_RDPCSTX_PHY_FUSE0
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
//RDPCSTX0_RDPCSTX_PHY_FUSE1
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
//RDPCSTX0_RDPCSTX_PHY_FUSE2
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
//RDPCSTX0_RDPCSTX_PHY_FUSE3
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
#define RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
//RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
#define RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
//RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
#define RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
//RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG
#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
#define RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
//RDPCSTX0_RDPCSTX_PHY_CNTL15
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
//RDPCSTX0_RDPCSTX_PHY_CNTL16
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
//RDPCSTX0_RDPCSTX_PHY_CNTL17
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
#define RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
//RDPCSTX0_RDPCSTX_DEBUG_CONFIG2
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
#define RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
//RDPCSTX0_RDPCS_CNTL3
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
#define RDPCSTX0_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
//RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
//RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
#define RDPCSTX0_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL


// addressBlock: dpcssys_dpcs0_rdpcstx1_dispdec
//RDPCSTX1_RDPCSTX_CNTL
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
#define RDPCSTX1_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
#define RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
//RDPCSTX1_RDPCSTX_CLOCK_CNTL
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
#define RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
//RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
#define RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA
#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
//RDPCSTX1_RDPCS_TX_CR_ADDR
#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
#define RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
//RDPCSTX1_RDPCS_TX_CR_DATA
#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
#define RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
//RDPCSTX1_RDPCS_TX_SRAM_CNTL
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
#define RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
//RDPCSTX1_RDPCSTX_SCRATCH
#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
#define RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
//RDPCSTX1_RDPCSTX_SPARE
#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
#define RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
//RDPCSTX1_RDPCSTX_CNTL2
#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
#define RDPCSTX1_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
//RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
//RDPCSTX1_RDPCSTX_DEBUG_CONFIG
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL0
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL1
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
//RDPCSTX1_RDPCSTX_PHY_CNTL2
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
//RDPCSTX1_RDPCSTX_PHY_CNTL3
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL4
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL5
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL6
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
//RDPCSTX1_RDPCSTX_PHY_CNTL7
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
#define RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
//RDPCSTX1_RDPCSTX_PHY_CNTL8
#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
//RDPCSTX1_RDPCSTX_PHY_CNTL9
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
#define RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL10
#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
//RDPCSTX1_RDPCSTX_PHY_CNTL11
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL12
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
//RDPCSTX1_RDPCSTX_PHY_CNTL13
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL14
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
//RDPCSTX1_RDPCSTX_PHY_FUSE0
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
//RDPCSTX1_RDPCSTX_PHY_FUSE1
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
//RDPCSTX1_RDPCSTX_PHY_FUSE2
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
//RDPCSTX1_RDPCSTX_PHY_FUSE3
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
#define RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
//RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL
#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
#define RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
//RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
#define RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
//RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG
#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
#define RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
//RDPCSTX1_RDPCSTX_PHY_CNTL15
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
//RDPCSTX1_RDPCSTX_PHY_CNTL16
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
//RDPCSTX1_RDPCSTX_PHY_CNTL17
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
#define RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
//RDPCSTX1_RDPCSTX_DEBUG_CONFIG2
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
#define RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
//RDPCSTX1_RDPCS_CNTL3
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
#define RDPCSTX1_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
//RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
//RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
#define RDPCSTX1_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL


// addressBlock: dpcssys_dpcs0_rdpcstx2_dispdec
//RDPCSTX2_RDPCSTX_CNTL
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
#define RDPCSTX2_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
#define RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
//RDPCSTX2_RDPCSTX_CLOCK_CNTL
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
#define RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
//RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
#define RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA
#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
//RDPCSTX2_RDPCS_TX_CR_ADDR
#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
#define RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
//RDPCSTX2_RDPCS_TX_CR_DATA
#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
#define RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
//RDPCSTX2_RDPCS_TX_SRAM_CNTL
#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
#define RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
//RDPCSTX2_RDPCSTX_SCRATCH
#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
#define RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
//RDPCSTX2_RDPCSTX_SPARE
#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
#define RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
//RDPCSTX2_RDPCSTX_CNTL2
#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
#define RDPCSTX2_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
//RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
//RDPCSTX2_RDPCSTX_DEBUG_CONFIG
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL0
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL1
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
#define RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
//RDPCSTX2_RDPCSTX_PHY_CNTL2
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
#define RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
//RDPCSTX2_RDPCSTX_PHY_CNTL3
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL4
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL5
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL6
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
//RDPCSTX2_RDPCSTX_PHY_CNTL7
#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
#define RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
//RDPCSTX2_RDPCSTX_PHY_CNTL8
#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
//RDPCSTX2_RDPCSTX_PHY_CNTL9
#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
#define RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL10
#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
//RDPCSTX2_RDPCSTX_PHY_CNTL11
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL12
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
#define RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
//RDPCSTX2_RDPCSTX_PHY_CNTL13
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL14
#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
//RDPCSTX2_RDPCSTX_PHY_FUSE0
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
//RDPCSTX2_RDPCSTX_PHY_FUSE1
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
//RDPCSTX2_RDPCSTX_PHY_FUSE2
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
//RDPCSTX2_RDPCSTX_PHY_FUSE3
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
#define RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
//RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL
#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
#define RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
//RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
#define RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
//RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG
#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
#define RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
//RDPCSTX2_RDPCSTX_PHY_CNTL15
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
//RDPCSTX2_RDPCSTX_PHY_CNTL16
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
//RDPCSTX2_RDPCSTX_PHY_CNTL17
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
#define RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
//RDPCSTX2_RDPCSTX_DEBUG_CONFIG2
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
#define RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
//RDPCSTX2_RDPCS_CNTL3
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
#define RDPCSTX2_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
//RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
//RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
#define RDPCSTX2_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL


// addressBlock: dpcssys_dpcs0_rdpcstx3_dispdec
//RDPCSTX3_RDPCSTX_CNTL
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
#define RDPCSTX3_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
#define RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
//RDPCSTX3_RDPCSTX_CLOCK_CNTL
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
#define RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
//RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
#define RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA
#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
//RDPCSTX3_RDPCS_TX_CR_ADDR
#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
#define RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
//RDPCSTX3_RDPCS_TX_CR_DATA
#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
#define RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
//RDPCSTX3_RDPCS_TX_SRAM_CNTL
#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
#define RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
//RDPCSTX3_RDPCSTX_SCRATCH
#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
#define RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
//RDPCSTX3_RDPCSTX_SPARE
#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
#define RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
//RDPCSTX3_RDPCSTX_CNTL2
#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
#define RDPCSTX3_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
//RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
//RDPCSTX3_RDPCSTX_DEBUG_CONFIG
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL0
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL1
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
#define RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
//RDPCSTX3_RDPCSTX_PHY_CNTL2
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
#define RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
//RDPCSTX3_RDPCSTX_PHY_CNTL3
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL4
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL5
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL6
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
//RDPCSTX3_RDPCSTX_PHY_CNTL7
#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
#define RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
//RDPCSTX3_RDPCSTX_PHY_CNTL8
#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
//RDPCSTX3_RDPCSTX_PHY_CNTL9
#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
#define RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL10
#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
//RDPCSTX3_RDPCSTX_PHY_CNTL11
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL12
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
#define RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
//RDPCSTX3_RDPCSTX_PHY_CNTL13
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL14
#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
//RDPCSTX3_RDPCSTX_PHY_FUSE0
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
//RDPCSTX3_RDPCSTX_PHY_FUSE1
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
//RDPCSTX3_RDPCSTX_PHY_FUSE2
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
//RDPCSTX3_RDPCSTX_PHY_FUSE3
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
#define RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
//RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL
#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
#define RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
//RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
#define RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
//RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG
#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
#define RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
//RDPCSTX3_RDPCSTX_PHY_CNTL15
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
//RDPCSTX3_RDPCSTX_PHY_CNTL16
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
//RDPCSTX3_RDPCSTX_PHY_CNTL17
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
#define RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
//RDPCSTX3_RDPCSTX_DEBUG_CONFIG2
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
#define RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
//RDPCSTX3_RDPCS_CNTL3
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
#define RDPCSTX3_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
//RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
//RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
#define RDPCSTX3_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL


// addressBlock: dpcssys_dpcs0_rdpcstx4_dispdec
//RDPCSTX4_RDPCSTX_CNTL
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT                                                   0x0
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT                                                   0x1
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x4
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x5
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x6
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK__SHIFT                                  0x7
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK__SHIFT                                                    0x8
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ__SHIFT                                                 0x9
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING__SHIFT                                             0xa
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT                                                  0xc
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT                                                  0xd
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT                                                  0xe
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT                                                  0xf
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB__SHIFT                                                  0x10
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB__SHIFT                                                  0x11
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB__SHIFT                                                  0x12
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB__SHIFT                                                  0x13
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT                                            0x14
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT                                                        0x19
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT                                                     0x1a
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT                                              0x1c
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT                                       0x1d
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT                                                0x1e
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT                                                     0x1f
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK                                                     0x00000001L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK                                                     0x00000002L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000010L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000020L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000040L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_BIT_ORDER_REVERSE_BEFORE_PACK_MASK                                    0x00000080L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_INTERRUPT_MASK_MASK                                                      0x00000100L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_REQ_MASK                                                   0x00000200L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_PLL_UPDATE_PENDING_MASK                                               0x00000400L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK                                                    0x00001000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK                                                    0x00002000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK                                                    0x00004000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK                                                    0x00008000L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE0_PACK_FROM_MSB_MASK                                                    0x00010000L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE1_PACK_FROM_MSB_MASK                                                    0x00020000L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE2_PACK_FROM_MSB_MASK                                                    0x00040000L
#define RDPCSTX4_RDPCSTX_CNTL__TX_LANE3_PACK_FROM_MSB_MASK                                                    0x00080000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK                                              0x01F00000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK                                                          0x02000000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK                                                       0x04000000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK                                                0x10000000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK                                         0x20000000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK                                                  0x40000000L
#define RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK                                                       0x80000000L
//RDPCSTX4_RDPCSTX_CLOCK_CNTL
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT                                               0x0
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN__SHIFT                                                  0x4
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN__SHIFT                                                  0x5
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN__SHIFT                                                  0x6
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN__SHIFT                                                  0x7
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS__SHIFT                                             0x8
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN__SHIFT                                                   0x9
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON__SHIFT                                             0xa
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN__SHIFT                                       0xb
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT                                            0xc
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT                                                  0xd
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT                                            0xe
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT                                              0x10
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT                                            0x14
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT                                                  0x15
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT                                            0x16
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK                                                 0x00000001L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX0_CLK_EN_MASK                                                    0x00000010L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX1_CLK_EN_MASK                                                    0x00000020L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX2_CLK_EN_MASK                                                    0x00000040L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX3_CLK_EN_MASK                                                    0x00000080L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_GATE_DIS_MASK                                               0x00000100L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_EN_MASK                                                     0x00000200L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_CLK_CLOCK_ON_MASK                                               0x00000400L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_TX_PHY_REF_ALT_CLK_EN_MASK                                         0x00000800L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK                                              0x00001000L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK                                                    0x00002000L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK                                              0x00004000L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK                                                0x00010000L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK                                              0x00100000L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK                                                    0x00200000L
#define RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK                                              0x00400000L
//RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT                                    0x0
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT                                 0x1
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT                                   0x2
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT                                       0x4
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT                                       0x5
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT                                       0x6
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT                                       0x7
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT                                        0x8
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT                             0x9
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT                               0xa
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT                                         0xc
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT                                  0x10
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT                            0x11
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT                              0x12
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT                                   0x14
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK                                      0x00000001L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK                                   0x00000002L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK                                     0x00000004L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK                                         0x00000010L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK                                         0x00000020L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK                                         0x00000040L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK                                         0x00000080L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK                                          0x00000100L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK                               0x00000200L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK                                 0x00000400L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK                                           0x00001000L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK                                    0x00010000L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK                              0x00020000L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK                                0x00040000L
#define RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK                                     0x00100000L
//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA
#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT                                       0x0
#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK                                         0x00000001L
//RDPCSTX4_RDPCS_TX_CR_ADDR
#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT                                                    0x0
#define RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK                                                      0x0000FFFFL
//RDPCSTX4_RDPCS_TX_CR_DATA
#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT                                                    0x0
#define RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK                                                      0x0000FFFFL
//RDPCSTX4_RDPCS_TX_SRAM_CNTL
#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT                                                 0x14
#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT                                               0x18
#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT                                           0x1c
#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK                                                   0x00100000L
#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK                                                 0x03000000L
#define RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK                                             0x30000000L
//RDPCSTX4_RDPCSTX_SCRATCH
#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT                                                      0x0
#define RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK                                                        0xFFFFFFFFL
//RDPCSTX4_RDPCSTX_SPARE
#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT                                                          0x0
#define RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK                                                            0xFFFFFFFFL
//RDPCSTX4_RDPCSTX_CNTL2
#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT                                            0x0
#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT                                             0x1
#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL__SHIFT                                                 0x2
#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK                                              0x00000001L
#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK                                               0x00000002L
#define RDPCSTX4_RDPCSTX_CNTL2__RDPCS_PHY_ENC_TYPE_SEL_MASK                                                   0x0000000CL
//RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT                      0x0
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS__SHIFT                   0x4
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT                      0x8
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK                        0x00000001L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_TX_CLK_DIS_MASK                     0x00000010L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK                        0x0000FF00L
//RDPCSTX4_RDPCSTX_DEBUG_CONFIG
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT                                                    0x0
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT                                        0x4
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT                                        0x7
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT                                          0x8
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT                                       0xf
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT                                          0x10
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT                                              0x18
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK                                                      0x00000001L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK                                          0x00000070L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK                                          0x00000080L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK                                            0x00001F00L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK                                         0x00008000L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK                                            0x00FF0000L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK                                                0xFF000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL0
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT                                                    0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT                                            0x1
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT                                          0x2
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT                                           0x3
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT                                                  0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT                                          0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT                                                0x9
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT                                                0x11
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT                                                0x12
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT                                              0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT                                               0x15
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT                                            0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT                                        0x19
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT                                               0x1c
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT                                             0x1d
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT                                                  0x1f
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK                                                      0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK                                              0x00000002L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK                                            0x00000004L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK                                             0x00000008L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK                                                    0x00000030L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK                                            0x00000100L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK                                                  0x00003E00L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK                                                  0x00020000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK                                                  0x00040000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK                                                0x00100000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK                                                 0x00200000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK                                              0x01000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK                                          0x02000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK                                                 0x10000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK                                               0x20000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK                                                    0x80000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL1
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT                                               0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT                                               0x1
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT                                           0x2
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT                                               0x3
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT                                           0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT                                              0x5
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT                                               0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT                                           0x7
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK                                                 0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK                                                 0x00000002L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK                                             0x00000004L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK                                                 0x00000008L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK                                             0x00000010L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK                                                0x00000020L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK                                                 0x00000040L
#define RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK                                             0x00000080L
//RDPCSTX4_RDPCSTX_PHY_CNTL2
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT                                                  0x3
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT                                 0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT                                 0x5
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT                                 0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT                                 0x7
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT                                 0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT                                 0x9
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT                                 0xa
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT                                 0xb
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK                                                    0x00000008L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK                                   0x00000010L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK                                   0x00000020L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK                                   0x00000040L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK                                   0x00000080L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK                                   0x00000100L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK                                   0x00000200L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK                                   0x00000400L
#define RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK                                   0x00000800L
//RDPCSTX4_RDPCSTX_PHY_CNTL3
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT                                             0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT                                           0x1
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT                                           0x2
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT                                           0x3
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT                                               0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT                                               0x5
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT                                             0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT                                           0x9
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT                                           0xa
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT                                           0xb
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT                                               0xc
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT                                               0xd
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT                                             0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT                                           0x11
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT                                           0x12
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT                                           0x13
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT                                               0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT                                               0x15
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT                                             0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT                                           0x19
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT                                           0x1a
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT                                           0x1b
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT                                               0x1c
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT                                               0x1d
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK                                               0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK                                             0x00000002L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK                                             0x00000004L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK                                             0x00000008L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK                                                 0x00000010L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK                                                 0x00000020L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK                                               0x00000100L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK                                             0x00000200L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK                                             0x00000400L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK                                             0x00000800L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK                                                 0x00001000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK                                                 0x00002000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK                                               0x00010000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK                                             0x00020000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK                                             0x00040000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK                                             0x00080000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK                                                 0x00100000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK                                                 0x00200000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK                                               0x01000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK                                             0x02000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK                                             0x04000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK                                             0x08000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK                                                 0x10000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK                                                 0x20000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL4
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT                                         0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT                                            0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT                                    0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT                                        0x7
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT                                         0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT                                            0xc
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT                                    0xe
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT                                        0xf
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT                                         0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT                                            0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT                                    0x16
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT                                        0x17
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT                                         0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT                                            0x1c
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT                                    0x1e
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT                                        0x1f
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK                                           0x00000007L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK                                              0x00000010L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK                                      0x00000040L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK                                          0x00000080L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK                                           0x00000700L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK                                              0x00001000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK                                      0x00004000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK                                          0x00008000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK                                           0x00070000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK                                              0x00100000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK                                      0x00400000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK                                          0x00800000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK                                           0x07000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK                                              0x10000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK                                      0x40000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK                                          0x80000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL5
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT                                               0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT                                              0x1
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT                                             0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT                                         0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT                                      0x7
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT                                               0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT                                              0x9
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT                                             0xc
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT                                         0xe
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT                                      0xf
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT                                               0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT                                              0x11
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT                                             0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT                                         0x16
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT                                      0x17
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT                                               0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT                                              0x19
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT                                             0x1c
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT                                         0x1e
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT                                      0x1f
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK                                                 0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK                                                0x0000000EL
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK                                               0x00000030L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK                                           0x00000040L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK                                        0x00000080L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK                                                 0x00000100L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK                                                0x00000E00L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK                                               0x00003000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK                                           0x00004000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK                                        0x00008000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK                                                 0x00010000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK                                                0x000E0000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK                                               0x00300000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK                                           0x00400000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK                                        0x00800000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK                                                 0x01000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK                                                0x0E000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK                                               0x30000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK                                           0x40000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK                                        0x80000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL6
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT                                            0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT                                           0x2
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT                                            0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT                                           0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT                                            0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT                                           0xa
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT                                            0xc
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT                                           0xe
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                                0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                            0x11
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                        0x12
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT                                            0x13
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT                                           0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK                                              0x00000003L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK                                             0x00000004L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK                                              0x00000030L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK                                             0x00000040L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK                                              0x00000300L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK                                             0x00000400L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK                                              0x00003000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK                                             0x00004000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                                  0x00010000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                              0x00020000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                          0x00040000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK                                              0x00080000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK                                             0x00100000L
//RDPCSTX4_RDPCSTX_PHY_CNTL7
#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT                                       0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT                                      0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK                                         0x0000FFFFL
#define RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK                                        0xFFFF0000L
//RDPCSTX4_RDPCSTX_PHY_CNTL8
#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT                                        0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK                                          0x000FFFFFL
//RDPCSTX4_RDPCSTX_PHY_CNTL9
#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT                                    0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT                                   0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK                                      0x001FFFFFL
#define RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK                                     0x01000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL10
#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT                                      0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK                                        0x0000FFFFL
//RDPCSTX4_RDPCSTX_PHY_CNTL11
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT                                     0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT                                     0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT                                    0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK                                       0x0000FFF0L
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK                                       0x00070000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK                                      0x00700000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x03000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL12
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT                                    0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT                                   0x2
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT                                     0x4
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT                                          0x7
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT                                         0x8
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK                                      0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK                                     0x00000004L
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK                                       0x00000070L
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK                                            0x00000080L
#define RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK                                           0x00000100L
//RDPCSTX4_RDPCSTX_PHY_CNTL13
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT                                 0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT                                     0x1c
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT                                       0x1d
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT                               0x1e
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK                                   0x0FF00000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK                                       0x10000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK                                         0x20000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK                                 0x40000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL14
#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT                                      0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT                                       0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT                                        0x1c
#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK                                        0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK                                         0x01000000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK                                          0x10000000L
//RDPCSTX4_RDPCSTX_PHY_FUSE0
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT                                           0xc
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT                                             0x12
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT                                        0x14
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT                                       0x16
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT                                             0x1d
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK                                               0x000C0000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK                                          0x00300000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK                                         0x1FC00000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK                                               0xE0000000L
//RDPCSTX4_RDPCSTX_PHY_FUSE1
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT                                           0xc
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT                                          0x12
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT                                         0x19
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK                                            0x01FC0000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK                                           0xFE000000L
//RDPCSTX4_RDPCSTX_PHY_FUSE2
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT                                           0xc
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT                                      0x17
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK                                        0x3F800000L
//RDPCSTX4_RDPCSTX_PHY_FUSE3
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT                                           0x0
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT                                            0x6
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT                                           0xc
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT                                             0x12
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT                                                0x18
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT                                            0x1a
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT                                      0x1d
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK                                             0x0000003FL
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK                                              0x00000FC0L
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK                                             0x0003F000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK                                               0x00FC0000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK                                                  0x03000000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK                                              0x1C000000L
#define RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK                                        0xE0000000L
//RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL
#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT                                        0x0
#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ__SHIFT                                   0x7
#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT                                        0x8
#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK                                          0x0000007FL
#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_CDR_VCO_LOWFREQ_MASK                                     0x00000080L
#define RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK                                          0x001FFF00L
//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT                         0x0
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT                       0x1
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT                       0x2
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT                       0x3
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT                           0x4
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT                           0x5
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT                         0x8
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT                       0x9
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT                       0xa
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT                       0xb
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT                           0xc
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT                           0xd
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT                         0x10
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT                       0x11
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT                       0x12
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT                       0x13
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT                           0x14
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT                           0x15
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT                         0x18
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT                       0x19
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT                       0x1a
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT                       0x1b
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT                           0x1c
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT                           0x1d
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK                           0x00000001L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK                         0x00000002L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK                         0x00000004L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK                         0x00000008L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK                             0x00000010L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK                             0x00000020L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK                           0x00000100L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK                         0x00000200L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK                         0x00000400L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK                         0x00000800L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK                             0x00001000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK                             0x00002000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK                           0x00010000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK                         0x00020000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK                         0x00040000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK                         0x00080000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK                             0x00100000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK                             0x00200000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK                           0x01000000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK                         0x02000000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK                         0x04000000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK                         0x08000000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK                             0x10000000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK                             0x20000000L
//RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT                        0x0
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT                       0x2
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT                        0x4
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT                       0x6
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT                        0x8
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT                       0xa
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT                        0xc
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT                       0xe
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT                            0x10
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT                        0x11
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT                    0x12
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT                        0x13
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT                       0x14
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK                          0x00000003L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK                         0x00000004L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK                          0x00000030L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK                         0x00000040L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK                          0x00000300L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK                         0x00000400L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK                          0x00003000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK                         0x00004000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK                              0x00010000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK                          0x00020000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK                      0x00040000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK                          0x00080000L
#define RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK                         0x00100000L
//RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG
#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT                                  0x0
#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT                                0x4
#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT                                  0x8
#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK                                    0x00000001L
#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK                                  0x00000010L
#define RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK                                    0x0000FF00L
//RDPCSTX4_RDPCSTX_PHY_CNTL15
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT                                        0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT                                      0x10
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT                                      0x11
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT                                      0x12
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT                                      0x13
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT                                              0x14
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK                                          0x00000001L
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK                                        0x00010000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK                                        0x00020000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK                                        0x00040000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK                                        0x00080000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK                                                0x00100000L
//RDPCSTX4_RDPCSTX_PHY_CNTL16
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT                                  0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT                                  0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT                                  0xc
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT                                  0x12
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT                                     0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK                                    0x0000001FL
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK                                    0x000007C0L
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK                                    0x0001F000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK                                    0x007C0000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK                                       0x1F000000L
//RDPCSTX4_RDPCSTX_PHY_CNTL17
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT                                   0x0
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT                                   0x6
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT                                   0xc
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT                                   0x12
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT                                      0x18
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK                                     0x0000001FL
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK                                     0x000007C0L
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK                                     0x0001F000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK                                     0x007C0000L
#define RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK                                        0x1F000000L
//RDPCSTX4_RDPCSTX_DEBUG_CONFIG2
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT                                            0x0
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT                                            0x4
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT                                            0x8
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT                                            0xc
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT                               0x10
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK                                              0x00000007L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK                                              0x00000070L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK                                              0x00000700L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK                                              0x00007000L
#define RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK                                 0x00010000L
//RDPCSTX4_RDPCS_CNTL3
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE__SHIFT                                               0x0
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE__SHIFT                                               0x8
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE__SHIFT                                               0x10
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE__SHIFT                                               0x18
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE0_BYTE_ORDER_CHANGE_MASK                                                 0x000000FFL
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE1_BYTE_ORDER_CHANGE_MASK                                                 0x0000FF00L
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE2_BYTE_ORDER_CHANGE_MASK                                                 0x00FF0000L
#define RDPCSTX4_RDPCS_CNTL3__TX_LANE3_BYTE_ORDER_CHANGE_MASK                                                 0xFF000000L
//RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD
#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD__SHIFT                           0x0
#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_ADDR_OVRRD__RDPCS_PLL_UPDATE_ADDR_OVRRD_MASK                             0x0003FFFFL
//RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD
#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD__SHIFT                           0x0
#define RDPCSTX4_RDPCS_TX_PLL_UPDATE_DATA_OVRRD__RDPCS_PLL_UPDATE_DATA_OVRRD_MASK                             0xFFFFFFFFL


// addressBlock: dpcssys_dpcs0_rdpcspipe0_dispdec
//RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
#define RDPCSPIPE0_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L


// addressBlock: dpcssys_dpcs0_rdpcspipe1_dispdec
//RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT                                            0x10
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT                                        0x11
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT                                    0x12
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK                                              0x00010000L
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK                                          0x00020000L
#define RDPCSPIPE1_RDPCSPIPE_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK                                      0x00040000L


// addressBlock: dpcssys_dcio_dcio_dispdec
//DC_GENERICA
#define DC_GENERICA__GENERICA_EN__SHIFT                                                                       0x0
#define DC_GENERICA__GENERICA_SEL__SHIFT                                                                      0x7
#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
#define DC_GENERICA__GENERICA_EN_MASK                                                                         0x00000001L
#define DC_GENERICA__GENERICA_SEL_MASK                                                                        0x00000F80L
#define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
#define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
//DC_GENERICB
#define DC_GENERICB__GENERICB_EN__SHIFT                                                                       0x0
#define DC_GENERICB__GENERICB_SEL__SHIFT                                                                      0x8
#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT                                                    0xc
#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT                                                     0x10
#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT                                                 0x14
#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT                                                0x18
#define DC_GENERICB__GENERICB_EN_MASK                                                                         0x00000001L
#define DC_GENERICB__GENERICB_SEL_MASK                                                                        0x00000F00L
#define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK                                                      0x0000F000L
#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK                                                       0x000F0000L
#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK                                                   0x00F00000L
#define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK                                                  0x0F000000L
//DCIO_CLOCK_CNTL
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL__SHIFT                                                             0x0
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS__SHIFT                                                       0x5
#define DCIO_CLOCK_CNTL__DCIO_TEST_CLK_SEL_MASK                                                               0x0000001FL
#define DCIO_CLOCK_CNTL__DISPCLK_R_DCIO_GATE_DIS_MASK                                                         0x00000020L
//DC_REF_CLK_CNTL
#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT                                                             0x0
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT                                                          0x8
#define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK                                                               0x00000003L
#define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK                                                            0x00000300L
//UNIPHYA_LINK_CNTL
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
#define UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
//UNIPHYA_CHANNEL_XBAR_CNTL
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
#define UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
//UNIPHYB_LINK_CNTL
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
#define UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
//UNIPHYB_CHANNEL_XBAR_CNTL
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
#define UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
//UNIPHYC_LINK_CNTL
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
#define UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
//UNIPHYC_CHANNEL_XBAR_CNTL
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
#define UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
//UNIPHYD_LINK_CNTL
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
#define UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
//UNIPHYD_CHANNEL_XBAR_CNTL
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
#define UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
//UNIPHYE_LINK_CNTL
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT                                                      0xc
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT                                                      0xd
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT                                                      0xe
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT                                                      0xf
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK                                                        0x00001000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK                                                        0x00002000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK                                                        0x00004000L
#define UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK                                                        0x00008000L
//UNIPHYE_CHANNEL_XBAR_CNTL
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT                                         0x0
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT                                         0x8
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT                                         0x10
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT                                         0x18
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK                                           0x00000003L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK                                           0x00000300L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK                                           0x00030000L
#define UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK                                           0x03000000L
//DCIO_WRCMD_DELAY
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY__SHIFT                                                                 0x18
#define DCIO_WRCMD_DELAY__UNIPHY_DELAY_MASK                                                                   0xFF000000L
//DC_PINSTRAPS
#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT                                                         0xd
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT                                                               0xe
#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT                                                            0x10
#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY__SHIFT                                                        0x11
#define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK                                                           0x00002000L
#define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK                                                                 0x0000C000L
#define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK                                                              0x00010000L
#define DC_PINSTRAPS__DC_PINSTRAPS_CONNECTIVITY_MASK                                                          0x000E0000L
//INTERCEPT_STATE
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE__SHIFT                                                      0x0
#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE__SHIFT                                                      0x1
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE__SHIFT                                                        0x4
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE__SHIFT                                                        0x5
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE__SHIFT                                                        0x6
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE__SHIFT                                                        0x7
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE__SHIFT                                                        0x8
#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE__SHIFT                                                        0x9
#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE__SHIFT                                                        0xa
#define INTERCEPT_STATE__PWRSEQ0_INTERCEPTB_STATE_MASK                                                        0x00000001L
#define INTERCEPT_STATE__PWRSEQ1_INTERCEPTB_STATE_MASK                                                        0x00000002L
#define INTERCEPT_STATE__DPCS0_INTERCEPTB_STATE_MASK                                                          0x00000010L
#define INTERCEPT_STATE__DPCS1_INTERCEPTB_STATE_MASK                                                          0x00000020L
#define INTERCEPT_STATE__DPCS2_INTERCEPTB_STATE_MASK                                                          0x00000040L
#define INTERCEPT_STATE__DPCS3_INTERCEPTB_STATE_MASK                                                          0x00000080L
#define INTERCEPT_STATE__DPCS4_INTERCEPTB_STATE_MASK                                                          0x00000100L
#define INTERCEPT_STATE__DPCS5_INTERCEPTB_STATE_MASK                                                          0x00000200L
#define INTERCEPT_STATE__DPCS6_INTERCEPTB_STATE_MASK                                                          0x00000400L
//DCIO_BL_PWM_FRAME_START_DISP_SEL
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x0
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL__SHIFT                            0x4
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM0_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000007L
#define DCIO_BL_PWM_FRAME_START_DISP_SEL__BL_PWM1_GRP1_FRAME_START_DISP_SEL_MASK                              0x00000070L
//DCIO_GSL_GENLK_PAD_CNTL
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL__SHIFT                                     0x4
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT                                               0x8
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL__SHIFT                                   0x14
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT                                             0x18
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_READY_SEL_MASK                                       0x00000030L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK                                                 0x00000300L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_READY_SEL_MASK                                     0x00300000L
#define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK                                               0x03000000L
//DCIO_GSL_SWAPLOCK_PAD_CNTL
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL__SHIFT                                 0x4
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT                                           0x8
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL__SHIFT                                 0x14
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT                                           0x18
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_READY_SEL_MASK                                   0x00000030L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK                                             0x00000300L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_READY_SEL_MASK                                   0x00300000L
#define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK                                             0x03000000L
//DCIO_SOFT_RESET
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET__SHIFT                                                            0x0
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET__SHIFT                                                            0x1
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET__SHIFT                                                            0x2
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET__SHIFT                                                            0x3
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET__SHIFT                                                            0x4
#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET__SHIFT                                                            0x5
#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET__SHIFT                                                            0x6
#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT                                                             0x8
#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT                                                             0x9
#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT                                                             0xa
#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT                                                             0xb
#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT                                                             0xc
#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT                                                             0xd
#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT                                                             0xe
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET__SHIFT                                                            0x10
#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET__SHIFT                                                            0x11
#define DCIO_SOFT_RESET__UNIPHYA_SOFT_RESET_MASK                                                              0x00000001L
#define DCIO_SOFT_RESET__UNIPHYB_SOFT_RESET_MASK                                                              0x00000002L
#define DCIO_SOFT_RESET__UNIPHYC_SOFT_RESET_MASK                                                              0x00000004L
#define DCIO_SOFT_RESET__UNIPHYD_SOFT_RESET_MASK                                                              0x00000008L
#define DCIO_SOFT_RESET__UNIPHYE_SOFT_RESET_MASK                                                              0x00000010L
#define DCIO_SOFT_RESET__UNIPHYF_SOFT_RESET_MASK                                                              0x00000020L
#define DCIO_SOFT_RESET__UNIPHYG_SOFT_RESET_MASK                                                              0x00000040L
#define DCIO_SOFT_RESET__DSYNCA_SOFT_RESET_MASK                                                               0x00000100L
#define DCIO_SOFT_RESET__DSYNCB_SOFT_RESET_MASK                                                               0x00000200L
#define DCIO_SOFT_RESET__DSYNCC_SOFT_RESET_MASK                                                               0x00000400L
#define DCIO_SOFT_RESET__DSYNCD_SOFT_RESET_MASK                                                               0x00000800L
#define DCIO_SOFT_RESET__DSYNCE_SOFT_RESET_MASK                                                               0x00001000L
#define DCIO_SOFT_RESET__DSYNCF_SOFT_RESET_MASK                                                               0x00002000L
#define DCIO_SOFT_RESET__DSYNCG_SOFT_RESET_MASK                                                               0x00004000L
#define DCIO_SOFT_RESET__PWRSEQ0_SOFT_RESET_MASK                                                              0x00010000L
#define DCIO_SOFT_RESET__PWRSEQ1_SOFT_RESET_MASK                                                              0x00020000L


// addressBlock: dpcssys_dcio_dcio_chip_dispdec
//DC_GPIO_GENERIC_MASK
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT                                                    0x0
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT                                                  0x1
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT                                                    0x2
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT                                                    0x4
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT                                                  0x5
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT                                                    0x6
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT                                                    0x8
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT                                                  0x9
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT                                                    0xa
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT                                                    0xc
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT                                                  0xd
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT                                                    0xe
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT                                                    0x10
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT                                                  0x11
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT                                                    0x12
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT                                                    0x14
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT                                                  0x15
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT                                                    0x16
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT                                                    0x18
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT                                                  0x19
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT                                                    0x1a
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN__SHIFT                                             0x1c
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK                                                      0x00000001L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK                                                    0x00000002L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK                                                      0x0000000CL
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK                                                      0x00000010L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK                                                    0x00000020L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK                                                      0x000000C0L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK                                                      0x00000100L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK                                                    0x00000200L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK                                                      0x00000C00L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK                                                      0x00001000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK                                                    0x00002000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK                                                      0x0000C000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK                                                      0x00010000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK                                                    0x00020000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK                                                      0x000C0000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK                                                      0x00100000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK                                                    0x00200000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK                                                      0x00C00000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK                                                      0x01000000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK                                                    0x02000000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK                                                      0x0C000000L
#define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_STRENGTH_SN_MASK                                               0xF0000000L
//DC_GPIO_GENERIC_A
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT                                                          0x0
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT                                                          0x8
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT                                                          0x10
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT                                                          0x14
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT                                                          0x15
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT                                                          0x16
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT                                                          0x17
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK                                                            0x00000001L
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK                                                            0x00000100L
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK                                                            0x00010000L
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK                                                            0x00100000L
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK                                                            0x00200000L
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK                                                            0x00400000L
#define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK                                                            0x00800000L
//DC_GPIO_GENERIC_EN
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT                                                        0x0
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT                                                        0x8
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT                                                        0x10
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT                                                        0x14
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT                                                        0x15
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT                                                        0x16
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT                                                        0x17
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK                                                          0x00000001L
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK                                                          0x00000100L
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK                                                          0x00010000L
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK                                                          0x00100000L
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK                                                          0x00200000L
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK                                                          0x00400000L
#define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK                                                          0x00800000L
//DC_GPIO_GENERIC_Y
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT                                                          0x0
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT                                                          0x8
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT                                                          0x10
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT                                                          0x14
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT                                                          0x15
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT                                                          0x16
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT                                                          0x17
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK                                                            0x00000001L
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK                                                            0x00000100L
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK                                                            0x00010000L
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK                                                            0x00100000L
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK                                                            0x00200000L
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK                                                            0x00400000L
#define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK                                                            0x00800000L
//DC_GPIO_DDC1_MASK
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT                                                        0x0
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT                                                       0x4
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT                                                        0x6
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT                                                       0x8
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT                                                      0xc
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT                                                       0xe
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT                                                               0x10
#define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT                                                                    0x14
#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT                                                         0x16
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT                                                         0x18
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT                                                        0x1c
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK                                                          0x00000001L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK                                                         0x00000010L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK                                                          0x00000040L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK                                                         0x00000100L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK                                                        0x00001000L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK                                                         0x00004000L
#define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK                                                                 0x00010000L
#define DC_GPIO_DDC1_MASK__AUX1_POL_MASK                                                                      0x00100000L
#define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK                                                           0x00400000L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK                                                           0x0F000000L
#define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK                                                          0xF0000000L
//DC_GPIO_DDC1_A
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT                                                              0x0
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT                                                             0x8
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK                                                                0x00000001L
#define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK                                                               0x00000100L
//DC_GPIO_DDC1_EN
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT                                                            0x0
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT                                                           0x8
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK                                                              0x00000001L
#define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK                                                             0x00000100L
//DC_GPIO_DDC1_Y
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT                                                              0x0
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT                                                             0x8
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK                                                                0x00000001L
#define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK                                                               0x00000100L
//DC_GPIO_DDC2_MASK
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT                                                        0x0
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT                                                       0x4
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT                                                        0x6
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT                                                       0x8
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT                                                      0xc
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT                                                       0xe
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT                                                               0x10
#define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT                                                                    0x14
#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT                                                         0x16
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT                                                         0x18
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT                                                        0x1c
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK                                                          0x00000001L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK                                                         0x00000010L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK                                                          0x00000040L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK                                                         0x00000100L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK                                                        0x00001000L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK                                                         0x00004000L
#define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK                                                                 0x00010000L
#define DC_GPIO_DDC2_MASK__AUX2_POL_MASK                                                                      0x00100000L
#define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK                                                           0x00400000L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK                                                           0x0F000000L
#define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK                                                          0xF0000000L
//DC_GPIO_DDC2_A
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT                                                              0x0
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT                                                             0x8
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK                                                                0x00000001L
#define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK                                                               0x00000100L
//DC_GPIO_DDC2_EN
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT                                                            0x0
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT                                                           0x8
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK                                                              0x00000001L
#define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK                                                             0x00000100L
//DC_GPIO_DDC2_Y
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT                                                              0x0
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT                                                             0x8
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK                                                                0x00000001L
#define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK                                                               0x00000100L
//DC_GPIO_DDC3_MASK
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT                                                        0x0
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT                                                       0x4
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT                                                        0x6
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT                                                       0x8
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT                                                      0xc
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT                                                       0xe
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT                                                               0x10
#define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT                                                                    0x14
#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT                                                         0x16
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT                                                         0x18
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT                                                        0x1c
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK                                                          0x00000001L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK                                                         0x00000010L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK                                                          0x00000040L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK                                                         0x00000100L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK                                                        0x00001000L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK                                                         0x00004000L
#define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK                                                                 0x00010000L
#define DC_GPIO_DDC3_MASK__AUX3_POL_MASK                                                                      0x00100000L
#define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK                                                           0x00400000L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK                                                           0x0F000000L
#define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK                                                          0xF0000000L
//DC_GPIO_DDC3_A
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT                                                              0x0
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT                                                             0x8
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK                                                                0x00000001L
#define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK                                                               0x00000100L
//DC_GPIO_DDC3_EN
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT                                                            0x0
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT                                                           0x8
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK                                                              0x00000001L
#define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK                                                             0x00000100L
//DC_GPIO_DDC3_Y
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT                                                              0x0
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT                                                             0x8
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK                                                                0x00000001L
#define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK                                                               0x00000100L
//DC_GPIO_DDC4_MASK
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT                                                        0x0
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT                                                       0x4
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT                                                        0x6
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT                                                       0x8
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT                                                      0xc
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT                                                       0xe
#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT                                                               0x10
#define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT                                                                    0x14
#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT                                                         0x16
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT                                                         0x18
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT                                                        0x1c
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK                                                          0x00000001L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK                                                         0x00000010L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK                                                          0x00000040L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK                                                         0x00000100L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK                                                        0x00001000L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK                                                         0x00004000L
#define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK                                                                 0x00010000L
#define DC_GPIO_DDC4_MASK__AUX4_POL_MASK                                                                      0x00100000L
#define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK                                                           0x00400000L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK                                                           0x0F000000L
#define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK                                                          0xF0000000L
//DC_GPIO_DDC4_A
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT                                                              0x0
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT                                                             0x8
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK                                                                0x00000001L
#define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK                                                               0x00000100L
//DC_GPIO_DDC4_EN
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT                                                            0x0
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT                                                           0x8
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK                                                              0x00000001L
#define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK                                                             0x00000100L
//DC_GPIO_DDC4_Y
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT                                                              0x0
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT                                                             0x8
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK                                                                0x00000001L
#define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK                                                               0x00000100L
//DC_GPIO_DDC5_MASK
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT                                                        0x0
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT                                                       0x4
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT                                                        0x6
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT                                                       0x8
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT                                                      0xc
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT                                                       0xe
#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT                                                               0x10
#define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT                                                                    0x14
#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT                                                         0x16
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT                                                         0x18
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT                                                        0x1c
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK                                                          0x00000001L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK                                                         0x00000010L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK                                                          0x00000040L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK                                                         0x00000100L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK                                                        0x00001000L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK                                                         0x00004000L
#define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK                                                                 0x00010000L
#define DC_GPIO_DDC5_MASK__AUX5_POL_MASK                                                                      0x00100000L
#define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK                                                           0x00400000L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK                                                           0x0F000000L
#define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK                                                          0xF0000000L
//DC_GPIO_DDC5_A
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT                                                              0x0
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT                                                             0x8
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK                                                                0x00000001L
#define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK                                                               0x00000100L
//DC_GPIO_DDC5_EN
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT                                                            0x0
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT                                                           0x8
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK                                                              0x00000001L
#define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK                                                             0x00000100L
//DC_GPIO_DDC5_Y
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT                                                              0x0
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT                                                             0x8
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK                                                                0x00000001L
#define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK                                                               0x00000100L
//DC_GPIO_DDCVGA_MASK
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT                                                    0x0
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT                                                    0x6
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT                                                   0x8
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT                                                  0xc
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT                                                   0xe
#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT                                                           0x10
#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT                                                                0x14
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT                                                     0x16
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT                                                     0x18
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT                                                    0x1c
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK                                                      0x00000001L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK                                                      0x00000040L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK                                                     0x00000100L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK                                                    0x00001000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK                                                     0x00004000L
#define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK                                                             0x00010000L
#define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK                                                                  0x00100000L
#define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK                                                       0x00400000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK                                                       0x0F000000L
#define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK                                                      0xF0000000L
//DC_GPIO_DDCVGA_A
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT                                                          0x0
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT                                                         0x8
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK                                                            0x00000001L
#define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK                                                           0x00000100L
//DC_GPIO_DDCVGA_EN
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT                                                        0x0
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT                                                       0x8
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK                                                          0x00000001L
#define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK                                                         0x00000100L
//DC_GPIO_DDCVGA_Y
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT                                                          0x0
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT                                                         0x8
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK                                                            0x00000001L
#define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK                                                           0x00000100L
//DC_GPIO_GENLK_MASK
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT                                                     0x0
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT                                                   0x1
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT                                                    0x3
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT                                                     0x4
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT                                                   0x8
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT                                                 0x9
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT                                                  0xb
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT                                                   0xc
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT                                                    0x10
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT                                                  0x11
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT                                                   0x13
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT                                                    0x14
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT                                                    0x18
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT                                                  0x19
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT                                                   0x1b
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT                                                    0x1c
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK                                                       0x00000001L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK                                                     0x00000002L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK                                                      0x00000008L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK                                                       0x00000030L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK                                                     0x00000100L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK                                                   0x00000200L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK                                                    0x00000800L
#define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK                                                     0x00003000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK                                                      0x00010000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK                                                    0x00020000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK                                                     0x00080000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK                                                      0x00300000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK                                                      0x01000000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK                                                    0x02000000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK                                                     0x08000000L
#define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK                                                      0x30000000L
//DC_GPIO_GENLK_A
#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT                                                           0x0
#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT                                                         0x8
#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT                                                          0x10
#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT                                                          0x18
#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK                                                             0x00000001L
#define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK                                                           0x00000100L
#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK                                                            0x00010000L
#define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK                                                            0x01000000L
//DC_GPIO_GENLK_EN
#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT                                                         0x0
#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT                                                       0x8
#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT                                                        0x10
#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT                                                        0x18
#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK                                                           0x00000001L
#define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK                                                         0x00000100L
#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK                                                          0x00010000L
#define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK                                                          0x01000000L
//DC_GPIO_GENLK_Y
#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT                                                           0x0
#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT                                                         0x8
#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT                                                          0x10
#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT                                                          0x18
#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK                                                             0x00000001L
#define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK                                                           0x00000100L
#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK                                                            0x00010000L
#define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK                                                            0x01000000L
//DC_GPIO_HPD_MASK
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT                                                            0x0
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT                                                          0x4
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT                                                            0x6
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT                                                            0x8
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT                                                          0x9
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT                                                            0xa
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT                                                            0x10
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT                                                          0x11
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT                                                            0x12
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT                                                            0x14
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT                                                          0x15
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT                                                            0x16
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT                                                            0x18
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT                                                          0x19
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT                                                            0x1a
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT                                                            0x1c
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT                                                          0x1d
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT                                                            0x1e
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK                                                              0x00000001L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK                                                            0x00000010L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK                                                              0x000000C0L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK                                                              0x00000100L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK                                                            0x00000200L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK                                                              0x00000C00L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK                                                              0x00010000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK                                                            0x00020000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK                                                              0x000C0000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK                                                              0x00100000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK                                                            0x00200000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK                                                              0x00C00000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK                                                              0x01000000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK                                                            0x02000000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK                                                              0x0C000000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK                                                              0x10000000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK                                                            0x20000000L
#define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK                                                              0xC0000000L
//DC_GPIO_HPD_A
#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT                                                                  0x0
#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT                                                                  0x8
#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT                                                                  0x10
#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT                                                                  0x18
#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT                                                                  0x1a
#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT                                                                  0x1c
#define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK                                                                    0x00000001L
#define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK                                                                    0x00000100L
#define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK                                                                    0x00010000L
#define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK                                                                    0x01000000L
#define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK                                                                    0x04000000L
#define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK                                                                    0x10000000L
//DC_GPIO_HPD_EN
#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT                                                                0x0
#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI__SHIFT                                                                 0x1
#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE__SHIFT                                                                 0x2
#define DC_GPIO_HPD_EN__HPD12_SPARE0__SHIFT                                                                   0x5
#define DC_GPIO_HPD_EN__HPD1_SEL0__SHIFT                                                                      0x6
#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT                                                                0x8
#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI__SHIFT                                                                 0x9
#define DC_GPIO_HPD_EN__HPD12_SPARE1__SHIFT                                                                   0xa
#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT                                                                0x10
#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI__SHIFT                                                                 0x11
#define DC_GPIO_HPD_EN__HPD34_SPARE0__SHIFT                                                                   0x12
#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT                                                                0x14
#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI__SHIFT                                                                 0x15
#define DC_GPIO_HPD_EN__HPD34_SPARE1__SHIFT                                                                   0x16
#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT                                                                0x18
#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI__SHIFT                                                                 0x19
#define DC_GPIO_HPD_EN__HPD56_SPARE0__SHIFT                                                                   0x1a
#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT                                                                0x1c
#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI__SHIFT                                                                 0x1d
#define DC_GPIO_HPD_EN__HPD56_SPARE1__SHIFT                                                                   0x1e
#define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK                                                                  0x00000001L
#define DC_GPIO_HPD_EN__HPD1_SCHMEN_PI_MASK                                                                   0x00000002L
#define DC_GPIO_HPD_EN__HPD1_SLEWNCORE_MASK                                                                   0x00000004L
#define DC_GPIO_HPD_EN__HPD12_SPARE0_MASK                                                                     0x00000020L
#define DC_GPIO_HPD_EN__HPD1_SEL0_MASK                                                                        0x00000040L
#define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK                                                                  0x00000100L
#define DC_GPIO_HPD_EN__HPD2_SCHMEN_PI_MASK                                                                   0x00000200L
#define DC_GPIO_HPD_EN__HPD12_SPARE1_MASK                                                                     0x00000400L
#define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK                                                                  0x00010000L
#define DC_GPIO_HPD_EN__HPD3_SCHMEN_PI_MASK                                                                   0x00020000L
#define DC_GPIO_HPD_EN__HPD34_SPARE0_MASK                                                                     0x00040000L
#define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK                                                                  0x00100000L
#define DC_GPIO_HPD_EN__HPD4_SCHMEN_PI_MASK                                                                   0x00200000L
#define DC_GPIO_HPD_EN__HPD34_SPARE1_MASK                                                                     0x00400000L
#define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK                                                                  0x01000000L
#define DC_GPIO_HPD_EN__HPD5_SCHMEN_PI_MASK                                                                   0x02000000L
#define DC_GPIO_HPD_EN__HPD56_SPARE0_MASK                                                                     0x04000000L
#define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK                                                                  0x10000000L
#define DC_GPIO_HPD_EN__HPD6_SCHMEN_PI_MASK                                                                   0x20000000L
#define DC_GPIO_HPD_EN__HPD56_SPARE1_MASK                                                                     0x40000000L
//DC_GPIO_HPD_Y
#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT                                                                  0x0
#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT                                                                  0x8
#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT                                                                  0x10
#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT                                                                  0x18
#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT                                                                  0x1a
#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT                                                                  0x1c
#define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK                                                                    0x00000001L
#define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK                                                                    0x00000100L
#define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK                                                                    0x00010000L
#define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK                                                                    0x01000000L
#define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK                                                                    0x04000000L
#define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK                                                                    0x10000000L
//DC_GPIO_PWRSEQ0_EN
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
#define DC_GPIO_PWRSEQ0_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
//DC_GPIO_PAD_STRENGTH_1
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT                                                      0x0
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT                                                      0x4
#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN__SHIFT                                                     0x10
#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP__SHIFT                                                     0x14
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT                                                       0x18
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT                                                       0x1c
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK                                                        0x0000000FL
#define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK                                                        0x000000F0L
#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SN_MASK                                                       0x000F0000L
#define DC_GPIO_PAD_STRENGTH_1__TX_HPD_STRENGTH_SP_MASK                                                       0x00F00000L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK                                                         0x0F000000L
#define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK                                                         0xF0000000L
//DC_GPIO_PAD_STRENGTH_2
#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT                                                            0x0
#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT                                                            0x4
#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH__SHIFT                                                  0x8
#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH__SHIFT                                                     0xc
#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL__SHIFT                                                         0x1e
#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK                                                              0x0000000FL
#define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK                                                              0x000000F0L
#define DC_GPIO_PAD_STRENGTH_2__EXT_RESET_DRVSTRENGTH_MASK                                                    0x00000700L
#define DC_GPIO_PAD_STRENGTH_2__REF_27_DRVSTRENGTH_MASK                                                       0x00007000L
#define DC_GPIO_PAD_STRENGTH_2__REF_27_SRC_SEL_MASK                                                           0xC0000000L
//PHY_AUX_CNTL
#define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT                                                                     0x9
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL__SHIFT                                                                   0xa
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL__SHIFT                                                                   0xc
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL__SHIFT                                                                   0xe
#define PHY_AUX_CNTL__AUX4_PAD_RXSEL__SHIFT                                                                   0x10
#define PHY_AUX_CNTL__AUX5_PAD_RXSEL__SHIFT                                                                   0x12
#define PHY_AUX_CNTL__AUX6_PAD_RXSEL__SHIFT                                                                   0x14
#define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK                                                                       0x00000200L
#define PHY_AUX_CNTL__AUX1_PAD_RXSEL_MASK                                                                     0x00000C00L
#define PHY_AUX_CNTL__AUX2_PAD_RXSEL_MASK                                                                     0x00003000L
#define PHY_AUX_CNTL__AUX3_PAD_RXSEL_MASK                                                                     0x0000C000L
#define PHY_AUX_CNTL__AUX4_PAD_RXSEL_MASK                                                                     0x00030000L
#define PHY_AUX_CNTL__AUX5_PAD_RXSEL_MASK                                                                     0x000C0000L
#define PHY_AUX_CNTL__AUX6_PAD_RXSEL_MASK                                                                     0x00300000L
//DC_GPIO_PWRSEQ1_EN
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN__SHIFT                                               0x14
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL__SHIFT                                              0x15
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN__SHIFT                                                  0x19
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL__SHIFT                                                 0x1a
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT                                                0x1d
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_EN_MASK                                                 0x00100000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_OTG_VSYNC_SEL_MASK                                                0x00E00000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_EN_MASK                                                    0x02000000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_BLON_OTG_VSYNC_SEL_MASK                                                   0x1C000000L
#define DC_GPIO_PWRSEQ1_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK                                                  0x20000000L
//DC_GPIO_TX12_EN
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN__SHIFT                                                      0x3
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN__SHIFT                                                      0x4
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN__SHIFT                                                      0x5
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN__SHIFT                                                      0x6
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN__SHIFT                                                      0x7
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN__SHIFT                                                      0x8
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN__SHIFT                                                      0x9
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICA_TX12_EN_MASK                                                        0x00000008L
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICB_TX12_EN_MASK                                                        0x00000010L
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICC_TX12_EN_MASK                                                        0x00000020L
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICD_TX12_EN_MASK                                                        0x00000040L
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICE_TX12_EN_MASK                                                        0x00000080L
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICF_TX12_EN_MASK                                                        0x00000100L
#define DC_GPIO_TX12_EN__DC_GPIO_GENERICG_TX12_EN_MASK                                                        0x00000200L
//DC_GPIO_AUX_CTRL_0
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL__SHIFT                                                   0x0
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL__SHIFT                                                   0x2
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL__SHIFT                                                   0x4
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL__SHIFT                                                   0x6
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL__SHIFT                                                   0x8
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL__SHIFT                                                   0xa
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL__SHIFT                                                 0xc
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN__SHIFT                                                     0x10
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN__SHIFT                                                     0x11
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN__SHIFT                                                     0x12
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN__SHIFT                                                     0x13
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN__SHIFT                                                     0x14
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN__SHIFT                                                     0x15
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN__SHIFT                                                   0x16
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL__SHIFT                                                    0x18
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL__SHIFT                                                    0x19
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL__SHIFT                                                    0x1a
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL__SHIFT                                                    0x1b
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL__SHIFT                                                    0x1c
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL__SHIFT                                                    0x1d
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL__SHIFT                                                  0x1e
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_FALLSLEWSEL_MASK                                                     0x00000003L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_FALLSLEWSEL_MASK                                                     0x0000000CL
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_FALLSLEWSEL_MASK                                                     0x00000030L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_FALLSLEWSEL_MASK                                                     0x000000C0L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_FALLSLEWSEL_MASK                                                     0x00000300L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_FALLSLEWSEL_MASK                                                     0x00000C00L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_FALLSLEWSEL_MASK                                                   0x00003000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCEN_MASK                                                       0x00010000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCEN_MASK                                                       0x00020000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCEN_MASK                                                       0x00040000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCEN_MASK                                                       0x00080000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCEN_MASK                                                       0x00100000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCEN_MASK                                                       0x00200000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCEN_MASK                                                     0x00400000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX1_SPIKERCSEL_MASK                                                      0x01000000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX2_SPIKERCSEL_MASK                                                      0x02000000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX3_SPIKERCSEL_MASK                                                      0x04000000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX4_SPIKERCSEL_MASK                                                      0x08000000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX5_SPIKERCSEL_MASK                                                      0x10000000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_AUX6_SPIKERCSEL_MASK                                                      0x20000000L
#define DC_GPIO_AUX_CTRL_0__DC_GPIO_DDCVGA_SPIKERCSEL_MASK                                                    0x40000000L
//DC_GPIO_AUX_CTRL_1
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9__SHIFT                                                       0x0
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1__SHIFT                                                       0x1
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9__SHIFT                                                       0x2
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1__SHIFT                                                       0x3
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9__SHIFT                                                       0x4
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1__SHIFT                                                       0x5
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9__SHIFT                                                       0x6
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1__SHIFT                                                       0x7
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN__SHIFT                                                      0x8
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN__SHIFT                                                      0x9
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN__SHIFT                                                      0xa
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN__SHIFT                                                      0xb
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL__SHIFT                                                       0xc
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE__SHIFT                                                       0xe
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN__SHIFT                                                       0x12
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL__SHIFT                                                       0x14
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL__SHIFT                                                       0x19
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL__SHIFT                                                       0x1a
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL__SHIFT                                                       0x1b
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL__SHIFT                                                       0x1c
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL__SHIFT                                                       0x1d
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL__SHIFT                                                     0x1e
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_0P9_MASK                                                         0x00000001L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_CSEL_1P1_MASK                                                         0x00000002L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_0P9_MASK                                                         0x00000004L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RSEL_1P1_MASK                                                         0x00000008L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_0P9_MASK                                                         0x00000010L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_CSEL_1P1_MASK                                                         0x00000020L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_0P9_MASK                                                         0x00000040L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RSEL_1P1_MASK                                                         0x00000080L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_BIASCRTEN_MASK                                                        0x00000100L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_BIASCRTEN_MASK                                                        0x00000200L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX_RESBIASEN_MASK                                                        0x00000400L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_I2C_RESBIASEN_MASK                                                        0x00000800L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX1_COMPSEL_MASK                                                         0x00001000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SPARE_MASK                                                         0x0000C000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_SLEWN_MASK                                                         0x00040000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_RXSEL_MASK                                                         0x00300000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX2_COMPSEL_MASK                                                         0x02000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX3_COMPSEL_MASK                                                         0x04000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX4_COMPSEL_MASK                                                         0x08000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX5_COMPSEL_MASK                                                         0x10000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_AUX6_COMPSEL_MASK                                                         0x20000000L
#define DC_GPIO_AUX_CTRL_1__DC_GPIO_DDCVGA_COMPSEL_MASK                                                       0x40000000L
//DC_GPIO_AUX_CTRL_2
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL__SHIFT                                                  0x0
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL__SHIFT                                                  0x2
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL__SHIFT                                                  0x4
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN__SHIFT                                                    0x8
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN__SHIFT                                                    0x9
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN__SHIFT                                                    0xa
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL__SHIFT                                                   0xc
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL__SHIFT                                                   0xd
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL__SHIFT                                                   0xe
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9__SHIFT                                                       0x10
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1__SHIFT                                                       0x11
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9__SHIFT                                                       0x12
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1__SHIFT                                                       0x13
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN__SHIFT                                                      0x14
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN__SHIFT                                                        0x18
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN__SHIFT                                                        0x19
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN__SHIFT                                                        0x1a
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN__SHIFT                                                      0x1b
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL__SHIFT                                                      0x1c
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL__SHIFT                                                      0x1d
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL__SHIFT                                                      0x1e
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_FALLSLEWSEL_MASK                                                    0x00000003L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_FALLSLEWSEL_MASK                                                    0x0000000CL
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_FALLSLEWSEL_MASK                                                    0x00000030L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCEN_MASK                                                      0x00000100L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCEN_MASK                                                      0x00000200L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCEN_MASK                                                      0x00000400L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SPIKERCSEL_MASK                                                     0x00001000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SPIKERCSEL_MASK                                                     0x00002000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SPIKERCSEL_MASK                                                     0x00004000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_0P9_MASK                                                         0x00010000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_CSEL_1P1_MASK                                                         0x00020000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_0P9_MASK                                                         0x00040000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RSEL_1P1_MASK                                                         0x00080000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_BIASCRTEN_MASK                                                        0x00100000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_SLEWN_MASK                                                          0x01000000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_SLEWN_MASK                                                          0x02000000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_SLEWN_MASK                                                          0x04000000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD_RESBIASEN_MASK                                                        0x08000000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD12_COMPSEL_MASK                                                        0x10000000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD34_COMPSEL_MASK                                                        0x20000000L
#define DC_GPIO_AUX_CTRL_2__DC_GPIO_HPD56_COMPSEL_MASK                                                        0x40000000L
//DC_GPIO_RXEN
#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN__SHIFT                                                            0x0
#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN__SHIFT                                                            0x1
#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN__SHIFT                                                            0x2
#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN__SHIFT                                                            0x3
#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN__SHIFT                                                            0x4
#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN__SHIFT                                                            0x5
#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN__SHIFT                                                            0x6
#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN__SHIFT                                                              0x8
#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN__SHIFT                                                              0x9
#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN__SHIFT                                                           0xa
#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN__SHIFT                                                         0xb
#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN__SHIFT                                                          0xc
#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN__SHIFT                                                          0xd
#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN__SHIFT                                                                0xe
#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN__SHIFT                                                                0xf
#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN__SHIFT                                                                0x10
#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN__SHIFT                                                                0x11
#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN__SHIFT                                                                0x12
#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN__SHIFT                                                                0x13
#define DC_GPIO_RXEN__DC_GPIO_GENERICA_RXEN_MASK                                                              0x00000001L
#define DC_GPIO_RXEN__DC_GPIO_GENERICB_RXEN_MASK                                                              0x00000002L
#define DC_GPIO_RXEN__DC_GPIO_GENERICC_RXEN_MASK                                                              0x00000004L
#define DC_GPIO_RXEN__DC_GPIO_GENERICD_RXEN_MASK                                                              0x00000008L
#define DC_GPIO_RXEN__DC_GPIO_GENERICE_RXEN_MASK                                                              0x00000010L
#define DC_GPIO_RXEN__DC_GPIO_GENERICF_RXEN_MASK                                                              0x00000020L
#define DC_GPIO_RXEN__DC_GPIO_GENERICG_RXEN_MASK                                                              0x00000040L
#define DC_GPIO_RXEN__DC_GPIO_HSYNCA_RXEN_MASK                                                                0x00000100L
#define DC_GPIO_RXEN__DC_GPIO_VSYNCA_RXEN_MASK                                                                0x00000200L
#define DC_GPIO_RXEN__DC_GPIO_GENLK_CLK_RXEN_MASK                                                             0x00000400L
#define DC_GPIO_RXEN__DC_GPIO_GENLK_VSYNC_RXEN_MASK                                                           0x00000800L
#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_A_RXEN_MASK                                                            0x00001000L
#define DC_GPIO_RXEN__DC_GPIO_SWAPLOCK_B_RXEN_MASK                                                            0x00002000L
#define DC_GPIO_RXEN__DC_GPIO_HPD1_RXEN_MASK                                                                  0x00004000L
#define DC_GPIO_RXEN__DC_GPIO_HPD2_RXEN_MASK                                                                  0x00008000L
#define DC_GPIO_RXEN__DC_GPIO_HPD3_RXEN_MASK                                                                  0x00010000L
#define DC_GPIO_RXEN__DC_GPIO_HPD4_RXEN_MASK                                                                  0x00020000L
#define DC_GPIO_RXEN__DC_GPIO_HPD5_RXEN_MASK                                                                  0x00040000L
#define DC_GPIO_RXEN__DC_GPIO_HPD6_RXEN_MASK                                                                  0x00080000L
//DC_GPIO_PULLUPEN
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN__SHIFT                                                       0x0
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN__SHIFT                                                       0x1
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN__SHIFT                                                       0x2
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN__SHIFT                                                       0x3
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN__SHIFT                                                       0x4
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN__SHIFT                                                       0x5
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN__SHIFT                                                       0x6
#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN__SHIFT                                                         0x8
#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN__SHIFT                                                         0x9
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN__SHIFT                                                           0xe
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN__SHIFT                                                           0xf
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN__SHIFT                                                           0x10
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN__SHIFT                                                           0x11
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN__SHIFT                                                           0x12
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN__SHIFT                                                           0x13
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICA_PU_EN_MASK                                                         0x00000001L
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICB_PU_EN_MASK                                                         0x00000002L
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICC_PU_EN_MASK                                                         0x00000004L
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICD_PU_EN_MASK                                                         0x00000008L
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICE_PU_EN_MASK                                                         0x00000010L
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICF_PU_EN_MASK                                                         0x00000020L
#define DC_GPIO_PULLUPEN__DC_GPIO_GENERICG_PU_EN_MASK                                                         0x00000040L
#define DC_GPIO_PULLUPEN__DC_GPIO_HSYNCA_PU_EN_MASK                                                           0x00000100L
#define DC_GPIO_PULLUPEN__DC_GPIO_VSYNCA_PU_EN_MASK                                                           0x00000200L
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD1_PU_EN_MASK                                                             0x00004000L
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD2_PU_EN_MASK                                                             0x00008000L
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD3_PU_EN_MASK                                                             0x00010000L
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD4_PU_EN_MASK                                                             0x00020000L
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD5_PU_EN_MASK                                                             0x00040000L
#define DC_GPIO_PULLUPEN__DC_GPIO_HPD6_PU_EN_MASK                                                             0x00080000L
//DC_GPIO_AUX_CTRL_3
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM__SHIFT                                                             0x0
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM__SHIFT                                                             0x1
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM__SHIFT                                                             0x2
#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM__SHIFT                                                             0x3
#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM__SHIFT                                                             0x4
#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM__SHIFT                                                             0x5
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP__SHIFT                                                            0x8
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP__SHIFT                                                            0x9
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP__SHIFT                                                            0xa
#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP__SHIFT                                                            0xb
#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP__SHIFT                                                            0xc
#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP__SHIFT                                                            0xd
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE__SHIFT                                                              0x10
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE__SHIFT                                                              0x12
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE__SHIFT                                                              0x14
#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE__SHIFT                                                              0x16
#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE__SHIFT                                                              0x18
#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE__SHIFT                                                              0x1a
#define DC_GPIO_AUX_CTRL_3__AUX1_NEN_RTERM_MASK                                                               0x00000001L
#define DC_GPIO_AUX_CTRL_3__AUX2_NEN_RTERM_MASK                                                               0x00000002L
#define DC_GPIO_AUX_CTRL_3__AUX3_NEN_RTERM_MASK                                                               0x00000004L
#define DC_GPIO_AUX_CTRL_3__AUX4_NEN_RTERM_MASK                                                               0x00000008L
#define DC_GPIO_AUX_CTRL_3__AUX5_NEN_RTERM_MASK                                                               0x00000010L
#define DC_GPIO_AUX_CTRL_3__AUX6_NEN_RTERM_MASK                                                               0x00000020L
#define DC_GPIO_AUX_CTRL_3__AUX1_DP_DN_SWAP_MASK                                                              0x00000100L
#define DC_GPIO_AUX_CTRL_3__AUX2_DP_DN_SWAP_MASK                                                              0x00000200L
#define DC_GPIO_AUX_CTRL_3__AUX3_DP_DN_SWAP_MASK                                                              0x00000400L
#define DC_GPIO_AUX_CTRL_3__AUX4_DP_DN_SWAP_MASK                                                              0x00000800L
#define DC_GPIO_AUX_CTRL_3__AUX5_DP_DN_SWAP_MASK                                                              0x00001000L
#define DC_GPIO_AUX_CTRL_3__AUX6_DP_DN_SWAP_MASK                                                              0x00002000L
#define DC_GPIO_AUX_CTRL_3__AUX1_HYS_TUNE_MASK                                                                0x00030000L
#define DC_GPIO_AUX_CTRL_3__AUX2_HYS_TUNE_MASK                                                                0x000C0000L
#define DC_GPIO_AUX_CTRL_3__AUX3_HYS_TUNE_MASK                                                                0x00300000L
#define DC_GPIO_AUX_CTRL_3__AUX4_HYS_TUNE_MASK                                                                0x00C00000L
#define DC_GPIO_AUX_CTRL_3__AUX5_HYS_TUNE_MASK                                                                0x03000000L
#define DC_GPIO_AUX_CTRL_3__AUX6_HYS_TUNE_MASK                                                                0x0C000000L
//DC_GPIO_AUX_CTRL_4
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL__SHIFT                                                              0x0
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL__SHIFT                                                              0x4
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL__SHIFT                                                              0x8
#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL__SHIFT                                                              0xc
#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL__SHIFT                                                              0x10
#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL__SHIFT                                                              0x14
#define DC_GPIO_AUX_CTRL_4__AUX1_AUX_CTRL_MASK                                                                0x0000000FL
#define DC_GPIO_AUX_CTRL_4__AUX2_AUX_CTRL_MASK                                                                0x000000F0L
#define DC_GPIO_AUX_CTRL_4__AUX3_AUX_CTRL_MASK                                                                0x00000F00L
#define DC_GPIO_AUX_CTRL_4__AUX4_AUX_CTRL_MASK                                                                0x0000F000L
#define DC_GPIO_AUX_CTRL_4__AUX5_AUX_CTRL_MASK                                                                0x000F0000L
#define DC_GPIO_AUX_CTRL_4__AUX6_AUX_CTRL_MASK                                                                0x00F00000L
//DC_GPIO_AUX_CTRL_5
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE__SHIFT                                                              0x0
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE__SHIFT                                                              0x2
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE__SHIFT                                                              0x4
#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE__SHIFT                                                              0x6
#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE__SHIFT                                                              0x8
#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE__SHIFT                                                              0xa
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE__SHIFT                                                           0xc
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE__SHIFT                                                           0xd
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE__SHIFT                                                           0xe
#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE__SHIFT                                                           0xf
#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE__SHIFT                                                           0x10
#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE__SHIFT                                                           0x11
#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN__SHIFT                                                        0x12
#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN__SHIFT                                                        0x13
#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN__SHIFT                                                        0x14
#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN__SHIFT                                                        0x15
#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN__SHIFT                                                        0x16
#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN__SHIFT                                                        0x17
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL__SHIFT                                                          0x18
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL__SHIFT                                                          0x19
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL__SHIFT                                                          0x1a
#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL__SHIFT                                                          0x1b
#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL__SHIFT                                                          0x1c
#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL__SHIFT                                                          0x1d
#define DC_GPIO_AUX_CTRL_5__AUX1_VOD_TUNE_MASK                                                                0x00000003L
#define DC_GPIO_AUX_CTRL_5__AUX2_VOD_TUNE_MASK                                                                0x0000000CL
#define DC_GPIO_AUX_CTRL_5__AUX3_VOD_TUNE_MASK                                                                0x00000030L
#define DC_GPIO_AUX_CTRL_5__AUX4_VOD_TUNE_MASK                                                                0x000000C0L
#define DC_GPIO_AUX_CTRL_5__AUX5_VOD_TUNE_MASK                                                                0x00000300L
#define DC_GPIO_AUX_CTRL_5__AUX6_VOD_TUNE_MASK                                                                0x00000C00L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD1_I2CMODE_MASK                                                             0x00001000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD2_I2CMODE_MASK                                                             0x00002000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD3_I2CMODE_MASK                                                             0x00004000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD4_I2CMODE_MASK                                                             0x00008000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD5_I2CMODE_MASK                                                             0x00010000L
#define DC_GPIO_AUX_CTRL_5__DDC_PAD6_I2CMODE_MASK                                                             0x00020000L
#define DC_GPIO_AUX_CTRL_5__DDC1_I2C_VPH_1V2_EN_MASK                                                          0x00040000L
#define DC_GPIO_AUX_CTRL_5__DDC2_I2C_VPH_1V2_EN_MASK                                                          0x00080000L
#define DC_GPIO_AUX_CTRL_5__DDC3_I2C_VPH_1V2_EN_MASK                                                          0x00100000L
#define DC_GPIO_AUX_CTRL_5__DDC4_I2C_VPH_1V2_EN_MASK                                                          0x00200000L
#define DC_GPIO_AUX_CTRL_5__DDC5_I2C_VPH_1V2_EN_MASK                                                          0x00400000L
#define DC_GPIO_AUX_CTRL_5__DDC6_I2C_VPH_1V2_EN_MASK                                                          0x00800000L
#define DC_GPIO_AUX_CTRL_5__DDC1_PAD_I2C_CTRL_MASK                                                            0x01000000L
#define DC_GPIO_AUX_CTRL_5__DDC2_PAD_I2C_CTRL_MASK                                                            0x02000000L
#define DC_GPIO_AUX_CTRL_5__DDC3_PAD_I2C_CTRL_MASK                                                            0x04000000L
#define DC_GPIO_AUX_CTRL_5__DDC4_PAD_I2C_CTRL_MASK                                                            0x08000000L
#define DC_GPIO_AUX_CTRL_5__DDC5_PAD_I2C_CTRL_MASK                                                            0x10000000L
#define DC_GPIO_AUX_CTRL_5__DDC6_PAD_I2C_CTRL_MASK                                                            0x20000000L
//AUXI2C_PAD_ALL_PWR_OK
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK__SHIFT                                                  0x0
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK__SHIFT                                                  0x1
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK__SHIFT                                                  0x2
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK__SHIFT                                                  0x3
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK__SHIFT                                                  0x4
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK__SHIFT                                                  0x5
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY1_ALL_PWR_OK_MASK                                                    0x00000001L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY2_ALL_PWR_OK_MASK                                                    0x00000002L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY3_ALL_PWR_OK_MASK                                                    0x00000004L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY4_ALL_PWR_OK_MASK                                                    0x00000008L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY5_ALL_PWR_OK_MASK                                                    0x00000010L
#define AUXI2C_PAD_ALL_PWR_OK__AUXI2C_PHY6_ALL_PWR_OK_MASK                                                    0x00000020L


// addressBlock: dpcssys_dcio_dcio_uniphy1_dispdec
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL


// addressBlock: dpcssys_dcio_dcio_uniphy2_dispdec
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL


// addressBlock: dpcssys_dcio_dcio_uniphy3_dispdec
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL


// addressBlock: dpcssys_dcio_dcio_uniphy4_dispdec
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                           0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK                             0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL
//DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT                          0x0
#define DCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK                            0xFFFFFFFFL


// addressBlock: dpcssys_cr0_rdpcstxcrind
//DPCSSYS_CR0_SUP_DIG_IDCODE_LO
#define DPCSSYS_CR0_SUP_DIG_IDCODE_LO__DATA__SHIFT                                                            0x0
//DPCSSYS_CR0_SUP_DIG_IDCODE_HI
#define DPCSSYS_CR0_SUP_DIG_IDCODE_HI__DATA__SHIFT                                                            0x0
//DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x0001L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x0004L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x01F0L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x0200L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x0400L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x0800L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x1000L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x2000L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x4000L
#define DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x0002L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x0004L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x0078L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x0080L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x0100L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x0200L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
//DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x0003L
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x00FCL
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x0700L
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x3800L
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x4000L
#define DPCSSYS_CR0_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x8000L
//DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0004L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0008L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0010L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x0040L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0080L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x0100L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x0200L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x0400L
#define DPCSSYS_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0xF800L
//DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x0070L
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x0080L
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x0700L
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x0800L
#define DPCSSYS_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR0_SUP_DIG_DEBUG
#define DPCSSYS_CR0_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define DPCSSYS_CR0_SUP_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                     0x3
#define DPCSSYS_CR0_SUP_DIG_DEBUG__RESERVED_15_4__SHIFT                                                       0x4
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR0_SUP_DIG_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x0001L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x0002L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x0004L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x0008L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x0010L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x0020L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x0040L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x0080L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x0100L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x0200L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x0400L
#define DPCSSYS_CR0_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0xF800L
//DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x0038L
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x01C0L
#define DPCSSYS_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0xFE00L
//DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR0_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0xFFFEL
//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                         0x0
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                          0x1
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                    0x2
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                     0x3
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                         0x4
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                           0x6
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                         0x0
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                    0x2
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                    0x3
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                    0x4
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                    0x5
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                    0x6
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_BG1
#define DPCSSYS_CR0_SUP_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                      0x0
#define DPCSSYS_CR0_SUP_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                    0x2
#define DPCSSYS_CR0_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
#define DPCSSYS_CR0_SUP_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                      0x5
#define DPCSSYS_CR0_SUP_ANA_BG1__RT_VREF_SEL__SHIFT                                                           0x7
#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR0_SUP_ANA_BG1__NC4_MASK                                                                     0x0010L
#define DPCSSYS_CR0_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR0_SUP_ANA_BG2
#define DPCSSYS_CR0_SUP_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                         0x0
#define DPCSSYS_CR0_SUP_ANA_BG2__SUP_CHOP_EN__SHIFT                                                           0x1
#define DPCSSYS_CR0_SUP_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                         0x2
#define DPCSSYS_CR0_SUP_ANA_BG2__VPHUD_SELREF__SHIFT                                                          0x3
#define DPCSSYS_CR0_SUP_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                       0x4
#define DPCSSYS_CR0_SUP_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                       0x5
#define DPCSSYS_CR0_SUP_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                 0x6
#define DPCSSYS_CR0_SUP_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR0_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                                0x0
#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                   0x7
#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_SUP_ANA_BG3
#define DPCSSYS_CR0_SUP_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                                0x0
#define DPCSSYS_CR0_SUP_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR0_SUP_ANA_BG3__NC7_4_MASK                                                                   0x00F0L
#define DPCSSYS_CR0_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x0100L
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x0001L
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x0002L
#define DPCSSYS_CR0_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG
#define DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define DPCSSYS_CR0_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x0002L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0xFFC0L
//DPCSSYS_CR0_SUP_DIG_RTUNE_STAT
#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x0C00L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0xF000L
//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x000FL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x00F0L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x0F00L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0xF000L
//DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x000FL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x01F0L
#define DPCSSYS_CR0_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0xFE00L
//DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x000FL
#define DPCSSYS_CR0_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x0100L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x0200L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x0100L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x0200L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x0001L
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x0006L
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x3FF0L
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x4000L
#define DPCSSYS_CR0_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_SUP_DIG_ANA_STAT
#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x0001L
#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x0002L
#define DPCSSYS_CR0_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0xFFFCL
//DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x0002L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x0004L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x0008L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x0010L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x0020L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x0040L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x0300L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x0400L
#define DPCSSYS_CR0_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0xF800L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR0_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR0_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_ATB1
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_ATB2
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR0_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_MISC1
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_MISC2
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_MISC3
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR0_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA
#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR0_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR0_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_ATB1
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_ATB2
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR0_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_MISC1
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_MISC2
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_MISC3
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR0_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_CLK_1
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_CLK_2
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR0_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL
#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_SQ
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR0_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_CAL1
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_CAL2
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1
#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA
#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR0_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR0_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_ATB1
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_ATB2
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR0_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_MISC1
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_MISC2
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_MISC3
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR0_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_CLK_1
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_CLK_2
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR0_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL
#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_SQ
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR0_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_CAL1
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_CAL2
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1
#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR0_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_ATB1
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_ATB2
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR0_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_MISC1
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_MISC2
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_MISC3
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR0_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND
#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__DATA__SHIFT                                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x0010L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x0300L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x0800L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x1000L
#define DPCSSYS_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
//DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x1E00L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x2000L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x4000L
#define DPCSSYS_CR0_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x8000L
//DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE
#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__DATA__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
#define DPCSSYS_CR0_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0xFFF0L
//DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE
#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__DATA__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR0_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR0_RAWCMN_DIG_OCLA
#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0xFFFCL
//DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x00E0L
#define DPCSSYS_CR0_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE
#define DPCSSYS_CR0_RAWCMN_DIG_PCS_RAW_ID_CODE__DATA__SHIFT                                                   0x0
//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1
#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0xFFFFL
//DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2
#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0xFFFFL
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x003FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x0010L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x0100L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x0008L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x001FL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR0_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR0_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR0_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR0_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR0_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_STATS
#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR0_RAWAONLANE0_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_STATS
#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR0_RAWAONLANE1_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_STATS
#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR0_RAWAONLANE2_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_STATS
#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR0_RAWAONLANE3_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_STATS
#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR0_RAWAONLANEX_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR0_SUPX_DIG_IDCODE_LO
#define DPCSSYS_CR0_SUPX_DIG_IDCODE_LO__DATA__SHIFT                                                           0x0
//DPCSSYS_CR0_SUPX_DIG_IDCODE_HI
#define DPCSSYS_CR0_SUPX_DIG_IDCODE_HI__DATA__SHIFT                                                           0x0
//DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x0001L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x0004L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x01F0L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x0200L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x0400L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x0800L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x1000L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x2000L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x4000L
#define DPCSSYS_CR0_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x8000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x0002L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x0004L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x0078L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x0080L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x0100L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0xFC00L
//DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x0003L
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x00FCL
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x0700L
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x3800L
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x4000L
#define DPCSSYS_CR0_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x8000L
//DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x0004L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x0010L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x0040L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x0080L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x0100L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x0400L
#define DPCSSYS_CR0_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0xF800L
//DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x0070L
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x0080L
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x0700L
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0xF000L
//DPCSSYS_CR0_SUPX_DIG_DEBUG
#define DPCSSYS_CR0_SUPX_DIG_DEBUG__DTB_SEL__SHIFT                                                            0x0
#define DPCSSYS_CR0_SUPX_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                    0x3
#define DPCSSYS_CR0_SUPX_DIG_DEBUG__RESERVED_15_4__SHIFT                                                      0x4
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_SUPX_DIG_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x0001L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x0002L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x0004L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x0008L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x0010L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x0020L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x0040L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x0080L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x0100L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x0200L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x0400L
#define DPCSSYS_CR0_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0xF800L
//DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x0038L
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x01C0L
#define DPCSSYS_CR0_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0xFE00L
//DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                        0x0
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                         0x1
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                   0x2
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                    0x3
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                        0x4
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                          0x6
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                        0x0
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                   0x1
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                   0x3
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                   0x4
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                   0x6
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_BG1
#define DPCSSYS_CR0_SUPX_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUPX_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
#define DPCSSYS_CR0_SUPX_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                     0x5
#define DPCSSYS_CR0_SUPX_ANA_BG1__RT_VREF_SEL__SHIFT                                                          0x7
#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR0_SUPX_ANA_BG1__NC4_MASK                                                                    0x0010L
#define DPCSSYS_CR0_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR0_SUPX_ANA_BG2
#define DPCSSYS_CR0_SUPX_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                        0x0
#define DPCSSYS_CR0_SUPX_ANA_BG2__SUP_CHOP_EN__SHIFT                                                          0x1
#define DPCSSYS_CR0_SUPX_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                        0x2
#define DPCSSYS_CR0_SUPX_ANA_BG2__VPHUD_SELREF__SHIFT                                                         0x3
#define DPCSSYS_CR0_SUPX_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                      0x4
#define DPCSSYS_CR0_SUPX_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                      0x5
#define DPCSSYS_CR0_SUPX_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                0x6
#define DPCSSYS_CR0_SUPX_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR0_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                               0x0
#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                  0x7
#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR0_SUPX_ANA_BG3
#define DPCSSYS_CR0_SUPX_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                               0x0
#define DPCSSYS_CR0_SUPX_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                  0x2
#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR0_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x00F0L
#define DPCSSYS_CR0_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x0200L
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x01FFL
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x00FFL
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x0100L
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x001FL
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x0020L
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x0001L
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x0002L
#define DPCSSYS_CR0_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                     0x1
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                      0x2
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                         0x3
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                        0x5
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                      0xf
//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x0002L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x0004L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x0038L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x0C00L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x003FL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x003FL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0xFFC0L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x000FL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x00F0L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x0F00L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0xF000L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x000FL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x01F0L
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0xFE00L
//DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x000FL
#define DPCSSYS_CR0_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x0100L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x0200L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x0100L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x0200L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x0001L
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x0006L
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x3FF0L
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR0_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_SUPX_DIG_ANA_STAT
#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x0001L
#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR0_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0xFFFCL
//DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x0002L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x0004L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x0010L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x0020L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x0040L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x0300L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR0_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA
#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR0_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR0_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR0_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_ATB1
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_ATB2
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR0_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_MISC1
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_MISC2
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_MISC3
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR0_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_CLK_1
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_CLK_2
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR0_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL
#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_SQ
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR0_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_CAL1
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_CAL2
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1
#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR0_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR0_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR0_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L


// addressBlock: dpcssys_cr1_rdpcstxcrind
//DPCSSYS_CR1_SUP_DIG_IDCODE_LO
#define DPCSSYS_CR1_SUP_DIG_IDCODE_LO__DATA__SHIFT                                                            0x0
//DPCSSYS_CR1_SUP_DIG_IDCODE_HI
#define DPCSSYS_CR1_SUP_DIG_IDCODE_HI__DATA__SHIFT                                                            0x0
//DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x0001L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x0004L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x01F0L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x0200L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x0400L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x0800L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x1000L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x2000L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x4000L
#define DPCSSYS_CR1_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x0002L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x0004L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x0078L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x0080L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x0100L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x0200L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
//DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x0003L
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x00FCL
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x0700L
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x3800L
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x4000L
#define DPCSSYS_CR1_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x8000L
//DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0004L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0008L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0010L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x0040L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0080L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x0100L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x0200L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x0400L
#define DPCSSYS_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0xF800L
//DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x0070L
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x0080L
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x0700L
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x0800L
#define DPCSSYS_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR1_SUP_DIG_DEBUG
#define DPCSSYS_CR1_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define DPCSSYS_CR1_SUP_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                     0x3
#define DPCSSYS_CR1_SUP_DIG_DEBUG__RESERVED_15_4__SHIFT                                                       0x4
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR1_SUP_DIG_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x0001L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x0002L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x0004L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x0008L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x0010L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x0020L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x0040L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x0080L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x0100L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x0200L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x0400L
#define DPCSSYS_CR1_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0xF800L
//DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x0038L
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x01C0L
#define DPCSSYS_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0xFE00L
//DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR1_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0xFFFEL
//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                         0x0
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                          0x1
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                    0x2
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                     0x3
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                         0x4
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                           0x6
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                         0x0
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                    0x2
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                    0x3
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                    0x4
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                    0x5
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                    0x6
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_BG1
#define DPCSSYS_CR1_SUP_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                      0x0
#define DPCSSYS_CR1_SUP_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                    0x2
#define DPCSSYS_CR1_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
#define DPCSSYS_CR1_SUP_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                      0x5
#define DPCSSYS_CR1_SUP_ANA_BG1__RT_VREF_SEL__SHIFT                                                           0x7
#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR1_SUP_ANA_BG1__NC4_MASK                                                                     0x0010L
#define DPCSSYS_CR1_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR1_SUP_ANA_BG2
#define DPCSSYS_CR1_SUP_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                         0x0
#define DPCSSYS_CR1_SUP_ANA_BG2__SUP_CHOP_EN__SHIFT                                                           0x1
#define DPCSSYS_CR1_SUP_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                         0x2
#define DPCSSYS_CR1_SUP_ANA_BG2__VPHUD_SELREF__SHIFT                                                          0x3
#define DPCSSYS_CR1_SUP_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                       0x4
#define DPCSSYS_CR1_SUP_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                       0x5
#define DPCSSYS_CR1_SUP_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                 0x6
#define DPCSSYS_CR1_SUP_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR1_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                                0x0
#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                   0x7
#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_SUP_ANA_BG3
#define DPCSSYS_CR1_SUP_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                                0x0
#define DPCSSYS_CR1_SUP_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR1_SUP_ANA_BG3__NC7_4_MASK                                                                   0x00F0L
#define DPCSSYS_CR1_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR1_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x0100L
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x0001L
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x0002L
#define DPCSSYS_CR1_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG
#define DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define DPCSSYS_CR1_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x0002L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0xFFC0L
//DPCSSYS_CR1_SUP_DIG_RTUNE_STAT
#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x0C00L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0xF000L
//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x000FL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x00F0L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x0F00L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0xF000L
//DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x000FL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x01F0L
#define DPCSSYS_CR1_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0xFE00L
//DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x000FL
#define DPCSSYS_CR1_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x0100L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x0200L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x0100L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x0200L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x0001L
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x0006L
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x3FF0L
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x4000L
#define DPCSSYS_CR1_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_SUP_DIG_ANA_STAT
#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x0001L
#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x0002L
#define DPCSSYS_CR1_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0xFFFCL
//DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x0002L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x0004L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x0008L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x0010L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x0020L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x0040L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x0300L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x0400L
#define DPCSSYS_CR1_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0xF800L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR1_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR1_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_ATB1
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_ATB2
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR1_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_MISC1
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_MISC2
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_MISC3
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR1_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA
#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR1_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR1_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_ATB1
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_ATB2
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR1_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_MISC1
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_MISC2
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_MISC3
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR1_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_CLK_1
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_CLK_2
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR1_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL
#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_SQ
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR1_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_CAL1
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_CAL2
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1
#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA
#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR1_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR1_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_ATB1
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_ATB2
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR1_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_MISC1
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_MISC2
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_MISC3
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR1_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_CLK_1
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_CLK_2
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR1_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL
#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_SQ
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR1_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_CAL1
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_CAL2
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1
#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR1_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_ATB1
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_ATB2
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR1_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_MISC1
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_MISC2
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_MISC3
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR1_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND
#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__DATA__SHIFT                                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x0010L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x0300L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x0800L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x1000L
#define DPCSSYS_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
//DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x1E00L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x2000L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x4000L
#define DPCSSYS_CR1_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x8000L
//DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE
#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__DATA__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
#define DPCSSYS_CR1_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0xFFF0L
//DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE
#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__DATA__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR1_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR1_RAWCMN_DIG_OCLA
#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0xFFFCL
//DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x00E0L
#define DPCSSYS_CR1_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE
#define DPCSSYS_CR1_RAWCMN_DIG_PCS_RAW_ID_CODE__DATA__SHIFT                                                   0x0
//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1
#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0xFFFFL
//DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2
#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0xFFFFL
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x003FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x0010L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x0100L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x0008L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x001FL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR1_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR1_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR1_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR1_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR1_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR1_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR1_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR1_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR1_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_STATS
#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR1_RAWAONLANE0_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_STATS
#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR1_RAWAONLANE1_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_STATS
#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR1_RAWAONLANE2_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_STATS
#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR1_RAWAONLANE3_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_STATS
#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR1_RAWAONLANEX_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR1_SUPX_DIG_IDCODE_LO
#define DPCSSYS_CR1_SUPX_DIG_IDCODE_LO__DATA__SHIFT                                                           0x0
//DPCSSYS_CR1_SUPX_DIG_IDCODE_HI
#define DPCSSYS_CR1_SUPX_DIG_IDCODE_HI__DATA__SHIFT                                                           0x0
//DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x0001L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x0004L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x01F0L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x0200L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x0400L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x0800L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x1000L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x2000L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x4000L
#define DPCSSYS_CR1_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x8000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x0002L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x0004L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x0078L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x0080L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x0100L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0xFC00L
//DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x0003L
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x00FCL
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x0700L
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x3800L
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x4000L
#define DPCSSYS_CR1_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x8000L
//DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x0004L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x0010L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x0040L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x0080L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x0100L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x0400L
#define DPCSSYS_CR1_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0xF800L
//DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x0070L
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x0080L
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x0700L
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0xF000L
//DPCSSYS_CR1_SUPX_DIG_DEBUG
#define DPCSSYS_CR1_SUPX_DIG_DEBUG__DTB_SEL__SHIFT                                                            0x0
#define DPCSSYS_CR1_SUPX_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                    0x3
#define DPCSSYS_CR1_SUPX_DIG_DEBUG__RESERVED_15_4__SHIFT                                                      0x4
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_SUPX_DIG_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x0001L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x0002L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x0004L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x0008L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x0010L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x0020L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x0040L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x0080L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x0100L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x0200L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x0400L
#define DPCSSYS_CR1_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0xF800L
//DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x0038L
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x01C0L
#define DPCSSYS_CR1_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0xFE00L
//DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                        0x0
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                         0x1
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                   0x2
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                    0x3
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                        0x4
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                          0x6
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                        0x0
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                   0x1
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                   0x3
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                   0x4
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                   0x6
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_BG1
#define DPCSSYS_CR1_SUPX_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUPX_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
#define DPCSSYS_CR1_SUPX_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                     0x5
#define DPCSSYS_CR1_SUPX_ANA_BG1__RT_VREF_SEL__SHIFT                                                          0x7
#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR1_SUPX_ANA_BG1__NC4_MASK                                                                    0x0010L
#define DPCSSYS_CR1_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR1_SUPX_ANA_BG2
#define DPCSSYS_CR1_SUPX_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                        0x0
#define DPCSSYS_CR1_SUPX_ANA_BG2__SUP_CHOP_EN__SHIFT                                                          0x1
#define DPCSSYS_CR1_SUPX_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                        0x2
#define DPCSSYS_CR1_SUPX_ANA_BG2__VPHUD_SELREF__SHIFT                                                         0x3
#define DPCSSYS_CR1_SUPX_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                      0x4
#define DPCSSYS_CR1_SUPX_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                      0x5
#define DPCSSYS_CR1_SUPX_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                0x6
#define DPCSSYS_CR1_SUPX_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR1_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                               0x0
#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                  0x7
#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR1_SUPX_ANA_BG3
#define DPCSSYS_CR1_SUPX_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                               0x0
#define DPCSSYS_CR1_SUPX_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                  0x2
#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR1_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x00F0L
#define DPCSSYS_CR1_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x0200L
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x01FFL
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x00FFL
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x0100L
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x001FL
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x0020L
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x0001L
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x0002L
#define DPCSSYS_CR1_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                     0x1
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                      0x2
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                         0x3
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                        0x5
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                      0xf
//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x0002L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x0004L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x0038L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x0C00L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x003FL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x003FL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0xFFC0L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x000FL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x00F0L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x0F00L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0xF000L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x000FL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x01F0L
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0xFE00L
//DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x000FL
#define DPCSSYS_CR1_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x0100L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x0200L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x0100L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x0200L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x0001L
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x0006L
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x3FF0L
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR1_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_SUPX_DIG_ANA_STAT
#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x0001L
#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR1_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0xFFFCL
//DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x0002L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x0004L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x0010L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x0020L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x0040L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x0300L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR1_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA
#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR1_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR1_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR1_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_ATB1
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_ATB2
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR1_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_MISC1
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_MISC2
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_MISC3
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR1_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_CLK_1
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_CLK_2
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR1_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL
#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_SQ
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR1_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_CAL1
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_CAL2
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1
#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR1_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR1_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR1_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L


// addressBlock: dpcssys_cr2_rdpcstxcrind
//DPCSSYS_CR2_SUP_DIG_IDCODE_LO
#define DPCSSYS_CR2_SUP_DIG_IDCODE_LO__DATA__SHIFT                                                            0x0
//DPCSSYS_CR2_SUP_DIG_IDCODE_HI
#define DPCSSYS_CR2_SUP_DIG_IDCODE_HI__DATA__SHIFT                                                            0x0
//DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x0001L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x0004L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x01F0L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x0200L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x0400L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x0800L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x1000L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x2000L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x4000L
#define DPCSSYS_CR2_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x0002L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x0004L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x0078L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x0080L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x0100L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x0200L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
//DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x0003L
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x00FCL
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x0700L
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x3800L
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x4000L
#define DPCSSYS_CR2_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x8000L
//DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0004L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0008L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0010L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x0040L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0080L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x0100L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x0200L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x0400L
#define DPCSSYS_CR2_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0xF800L
//DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x0070L
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x0080L
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x0700L
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x0800L
#define DPCSSYS_CR2_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR2_SUP_DIG_DEBUG
#define DPCSSYS_CR2_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define DPCSSYS_CR2_SUP_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                     0x3
#define DPCSSYS_CR2_SUP_DIG_DEBUG__RESERVED_15_4__SHIFT                                                       0x4
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR2_SUP_DIG_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x0001L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x0002L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x0004L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x0008L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x0010L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x0020L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x0040L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x0080L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x0100L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x0200L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x0400L
#define DPCSSYS_CR2_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0xF800L
//DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x0038L
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x01C0L
#define DPCSSYS_CR2_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0xFE00L
//DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR2_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0xFFFEL
//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                         0x0
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                          0x1
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                    0x2
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                     0x3
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                         0x4
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                           0x6
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                         0x0
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                    0x2
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                    0x3
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                    0x4
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                    0x5
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                    0x6
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_BG1
#define DPCSSYS_CR2_SUP_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                      0x0
#define DPCSSYS_CR2_SUP_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                    0x2
#define DPCSSYS_CR2_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
#define DPCSSYS_CR2_SUP_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                      0x5
#define DPCSSYS_CR2_SUP_ANA_BG1__RT_VREF_SEL__SHIFT                                                           0x7
#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR2_SUP_ANA_BG1__NC4_MASK                                                                     0x0010L
#define DPCSSYS_CR2_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR2_SUP_ANA_BG2
#define DPCSSYS_CR2_SUP_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                         0x0
#define DPCSSYS_CR2_SUP_ANA_BG2__SUP_CHOP_EN__SHIFT                                                           0x1
#define DPCSSYS_CR2_SUP_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                         0x2
#define DPCSSYS_CR2_SUP_ANA_BG2__VPHUD_SELREF__SHIFT                                                          0x3
#define DPCSSYS_CR2_SUP_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                       0x4
#define DPCSSYS_CR2_SUP_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                       0x5
#define DPCSSYS_CR2_SUP_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                 0x6
#define DPCSSYS_CR2_SUP_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR2_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                                0x0
#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                   0x7
#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_SUP_ANA_BG3
#define DPCSSYS_CR2_SUP_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                                0x0
#define DPCSSYS_CR2_SUP_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR2_SUP_ANA_BG3__NC7_4_MASK                                                                   0x00F0L
#define DPCSSYS_CR2_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR2_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR2_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x0100L
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x0001L
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x0002L
#define DPCSSYS_CR2_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG
#define DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define DPCSSYS_CR2_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x0002L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0xFFC0L
//DPCSSYS_CR2_SUP_DIG_RTUNE_STAT
#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x0C00L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0xF000L
//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x000FL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x00F0L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x0F00L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0xF000L
//DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x000FL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x01F0L
#define DPCSSYS_CR2_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0xFE00L
//DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x000FL
#define DPCSSYS_CR2_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x0100L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x0200L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x0100L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x0200L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x0001L
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x0006L
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x3FF0L
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x4000L
#define DPCSSYS_CR2_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_SUP_DIG_ANA_STAT
#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x0001L
#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x0002L
#define DPCSSYS_CR2_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0xFFFCL
//DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x0002L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x0004L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x0008L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x0010L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x0020L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x0040L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x0300L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x0400L
#define DPCSSYS_CR2_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0xF800L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR2_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR2_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR2_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR2_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR2_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_ATB1
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_ATB2
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR2_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_MISC1
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_MISC2
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_MISC3
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR2_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA
#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR2_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR2_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR2_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR2_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR2_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR2_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR2_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR2_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_ATB1
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_ATB2
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR2_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_MISC1
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_MISC2
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_MISC3
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR2_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_CLK_1
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_CLK_2
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR2_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL
#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_SQ
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR2_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_CAL1
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_CAL2
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1
#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA
#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR2_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR2_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR2_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR2_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR2_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR2_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR2_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR2_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_ATB1
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_ATB2
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR2_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_MISC1
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_MISC2
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_MISC3
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR2_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_CLK_1
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_CLK_2
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR2_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL
#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_SQ
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR2_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_CAL1
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_CAL2
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1
#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR2_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR2_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR2_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR2_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_ATB1
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_ATB2
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR2_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_MISC1
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_MISC2
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_MISC3
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR2_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND
#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__DATA__SHIFT                                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x0010L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x0300L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x0800L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x1000L
#define DPCSSYS_CR2_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
//DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x1E00L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x2000L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x4000L
#define DPCSSYS_CR2_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x8000L
//DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE
#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__DATA__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
#define DPCSSYS_CR2_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0xFFF0L
//DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE
#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__DATA__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR2_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR2_RAWCMN_DIG_OCLA
#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0xFFFCL
//DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x00E0L
#define DPCSSYS_CR2_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE
#define DPCSSYS_CR2_RAWCMN_DIG_PCS_RAW_ID_CODE__DATA__SHIFT                                                   0x0
//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1
#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0xFFFFL
//DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2
#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0xFFFFL
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x003FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x0010L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x0100L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x0008L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x001FL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR2_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR2_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR2_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR2_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR2_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR2_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR2_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR2_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR2_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_STATS
#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR2_RAWAONLANE0_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_STATS
#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR2_RAWAONLANE1_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_STATS
#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR2_RAWAONLANE2_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_STATS
#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR2_RAWAONLANE3_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_STATS
#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR2_RAWAONLANEX_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR2_SUPX_DIG_IDCODE_LO
#define DPCSSYS_CR2_SUPX_DIG_IDCODE_LO__DATA__SHIFT                                                           0x0
//DPCSSYS_CR2_SUPX_DIG_IDCODE_HI
#define DPCSSYS_CR2_SUPX_DIG_IDCODE_HI__DATA__SHIFT                                                           0x0
//DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x0001L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x0004L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x01F0L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x0200L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x0400L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x0800L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x1000L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x2000L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x4000L
#define DPCSSYS_CR2_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x8000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x0002L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x0004L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x0078L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x0080L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x0100L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0xFC00L
//DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x0003L
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x00FCL
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x0700L
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x3800L
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x4000L
#define DPCSSYS_CR2_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x8000L
//DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x0004L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x0010L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x0040L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x0080L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x0100L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x0400L
#define DPCSSYS_CR2_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0xF800L
//DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x0070L
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x0080L
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x0700L
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0xF000L
//DPCSSYS_CR2_SUPX_DIG_DEBUG
#define DPCSSYS_CR2_SUPX_DIG_DEBUG__DTB_SEL__SHIFT                                                            0x0
#define DPCSSYS_CR2_SUPX_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                    0x3
#define DPCSSYS_CR2_SUPX_DIG_DEBUG__RESERVED_15_4__SHIFT                                                      0x4
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_SUPX_DIG_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x0001L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x0002L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x0004L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x0008L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x0010L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x0020L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x0040L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x0080L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x0100L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x0200L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x0400L
#define DPCSSYS_CR2_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0xF800L
//DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x0038L
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x01C0L
#define DPCSSYS_CR2_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0xFE00L
//DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                        0x0
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                         0x1
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                   0x2
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                    0x3
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                        0x4
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                          0x6
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                        0x0
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                   0x1
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                   0x3
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                   0x4
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                   0x6
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_BG1
#define DPCSSYS_CR2_SUPX_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUPX_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
#define DPCSSYS_CR2_SUPX_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                     0x5
#define DPCSSYS_CR2_SUPX_ANA_BG1__RT_VREF_SEL__SHIFT                                                          0x7
#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR2_SUPX_ANA_BG1__NC4_MASK                                                                    0x0010L
#define DPCSSYS_CR2_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR2_SUPX_ANA_BG2
#define DPCSSYS_CR2_SUPX_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                        0x0
#define DPCSSYS_CR2_SUPX_ANA_BG2__SUP_CHOP_EN__SHIFT                                                          0x1
#define DPCSSYS_CR2_SUPX_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                        0x2
#define DPCSSYS_CR2_SUPX_ANA_BG2__VPHUD_SELREF__SHIFT                                                         0x3
#define DPCSSYS_CR2_SUPX_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                      0x4
#define DPCSSYS_CR2_SUPX_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                      0x5
#define DPCSSYS_CR2_SUPX_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                0x6
#define DPCSSYS_CR2_SUPX_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR2_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                               0x0
#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                  0x7
#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR2_SUPX_ANA_BG3
#define DPCSSYS_CR2_SUPX_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                               0x0
#define DPCSSYS_CR2_SUPX_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                  0x2
#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR2_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x00F0L
#define DPCSSYS_CR2_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x0200L
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x01FFL
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x00FFL
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x0100L
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x001FL
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x0020L
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x0001L
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x0002L
#define DPCSSYS_CR2_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                     0x1
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                      0x2
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                         0x3
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                        0x5
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                      0xf
//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x0002L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x0004L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x0038L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x0C00L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x003FL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x003FL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0xFFC0L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x000FL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x00F0L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x0F00L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0xF000L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x000FL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x01F0L
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0xFE00L
//DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x000FL
#define DPCSSYS_CR2_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x0100L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x0200L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x0100L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x0200L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x0001L
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x0006L
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x3FF0L
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR2_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_SUPX_DIG_ANA_STAT
#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x0001L
#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR2_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0xFFFCL
//DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x0002L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x0004L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x0010L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x0020L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x0040L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x0300L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR2_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA
#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR2_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR2_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR2_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR2_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR2_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR2_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR2_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR2_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR2_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_ATB1
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_ATB2
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR2_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_MISC1
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_MISC2
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_MISC3
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR2_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_CLK_1
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_CLK_2
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR2_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL
#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_SQ
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR2_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_CAL1
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_CAL2
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1
#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR2_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR2_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR2_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L


// addressBlock: dpcssys_cr3_rdpcstxcrind
//DPCSSYS_CR3_SUP_DIG_IDCODE_LO
#define DPCSSYS_CR3_SUP_DIG_IDCODE_LO__DATA__SHIFT                                                            0x0
//DPCSSYS_CR3_SUP_DIG_IDCODE_HI
#define DPCSSYS_CR3_SUP_DIG_IDCODE_HI__DATA__SHIFT                                                            0x0
//DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x0001L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x0004L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x01F0L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x0200L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x0400L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x0800L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x1000L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x2000L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x4000L
#define DPCSSYS_CR3_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x0002L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x0004L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x0078L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x0080L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x0100L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x0200L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
//DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x0003L
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x00FCL
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x0700L
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x3800L
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x4000L
#define DPCSSYS_CR3_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x8000L
//DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0004L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0008L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0010L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x0040L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0080L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x0100L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x0200L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x0400L
#define DPCSSYS_CR3_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0xF800L
//DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x0070L
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x0080L
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x0700L
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x0800L
#define DPCSSYS_CR3_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR3_SUP_DIG_DEBUG
#define DPCSSYS_CR3_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define DPCSSYS_CR3_SUP_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                     0x3
#define DPCSSYS_CR3_SUP_DIG_DEBUG__RESERVED_15_4__SHIFT                                                       0x4
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR3_SUP_DIG_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x0001L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x0002L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x0004L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x0008L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x0010L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x0020L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x0040L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x0080L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x0100L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x0200L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x0400L
#define DPCSSYS_CR3_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0xF800L
//DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x0038L
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x01C0L
#define DPCSSYS_CR3_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0xFE00L
//DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR3_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0xFFFEL
//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                         0x0
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                          0x1
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                    0x2
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                     0x3
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                         0x4
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                           0x6
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                         0x0
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                    0x2
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                    0x3
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                    0x4
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                    0x5
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                    0x6
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_BG1
#define DPCSSYS_CR3_SUP_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                      0x0
#define DPCSSYS_CR3_SUP_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                    0x2
#define DPCSSYS_CR3_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
#define DPCSSYS_CR3_SUP_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                      0x5
#define DPCSSYS_CR3_SUP_ANA_BG1__RT_VREF_SEL__SHIFT                                                           0x7
#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR3_SUP_ANA_BG1__NC4_MASK                                                                     0x0010L
#define DPCSSYS_CR3_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR3_SUP_ANA_BG2
#define DPCSSYS_CR3_SUP_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                         0x0
#define DPCSSYS_CR3_SUP_ANA_BG2__SUP_CHOP_EN__SHIFT                                                           0x1
#define DPCSSYS_CR3_SUP_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                         0x2
#define DPCSSYS_CR3_SUP_ANA_BG2__VPHUD_SELREF__SHIFT                                                          0x3
#define DPCSSYS_CR3_SUP_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                       0x4
#define DPCSSYS_CR3_SUP_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                       0x5
#define DPCSSYS_CR3_SUP_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                 0x6
#define DPCSSYS_CR3_SUP_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR3_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                                0x0
#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                   0x7
#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_SUP_ANA_BG3
#define DPCSSYS_CR3_SUP_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                                0x0
#define DPCSSYS_CR3_SUP_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR3_SUP_ANA_BG3__NC7_4_MASK                                                                   0x00F0L
#define DPCSSYS_CR3_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR3_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR3_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x0100L
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x0001L
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x0002L
#define DPCSSYS_CR3_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG
#define DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define DPCSSYS_CR3_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x0002L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0xFFC0L
//DPCSSYS_CR3_SUP_DIG_RTUNE_STAT
#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x0C00L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0xF000L
//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x000FL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x00F0L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x0F00L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0xF000L
//DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x000FL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x01F0L
#define DPCSSYS_CR3_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0xFE00L
//DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x000FL
#define DPCSSYS_CR3_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x0100L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x0200L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x0100L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x0200L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x0001L
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x0006L
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x3FF0L
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x4000L
#define DPCSSYS_CR3_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_SUP_DIG_ANA_STAT
#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x0001L
#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x0002L
#define DPCSSYS_CR3_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0xFFFCL
//DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x0002L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x0004L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x0008L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x0010L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x0020L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x0040L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x0300L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x0400L
#define DPCSSYS_CR3_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0xF800L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR3_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR3_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR3_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR3_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR3_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_ATB1
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_ATB2
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR3_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_MISC1
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_MISC2
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_MISC3
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR3_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA
#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR3_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR3_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR3_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR3_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR3_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR3_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR3_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR3_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_ATB1
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_ATB2
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR3_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_MISC1
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_MISC2
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_MISC3
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR3_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_CLK_1
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_CLK_2
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR3_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL
#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_SQ
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR3_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_CAL1
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_CAL2
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1
#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA
#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR3_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR3_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR3_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR3_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR3_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR3_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR3_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR3_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_ATB1
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_ATB2
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR3_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_MISC1
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_MISC2
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_MISC3
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR3_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_CLK_1
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_CLK_2
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR3_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL
#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_SQ
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR3_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_CAL1
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_CAL2
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1
#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR3_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR3_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR3_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR3_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_ATB1
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_ATB2
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR3_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_MISC1
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_MISC2
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_MISC3
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR3_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND
#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__DATA__SHIFT                                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x0010L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x0300L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x0800L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x1000L
#define DPCSSYS_CR3_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
//DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x1E00L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x2000L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x4000L
#define DPCSSYS_CR3_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x8000L
//DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE
#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__DATA__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
#define DPCSSYS_CR3_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0xFFF0L
//DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE
#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__DATA__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR3_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR3_RAWCMN_DIG_OCLA
#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0xFFFCL
//DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x00E0L
#define DPCSSYS_CR3_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE
#define DPCSSYS_CR3_RAWCMN_DIG_PCS_RAW_ID_CODE__DATA__SHIFT                                                   0x0
//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1
#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0xFFFFL
//DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2
#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0xFFFFL
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x003FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x0010L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x0100L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x0008L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x001FL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR3_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR3_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR3_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR3_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR3_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR3_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR3_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR3_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR3_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_STATS
#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR3_RAWAONLANE0_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_STATS
#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR3_RAWAONLANE1_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_STATS
#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR3_RAWAONLANE2_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_STATS
#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR3_RAWAONLANE3_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_STATS
#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR3_RAWAONLANEX_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR3_SUPX_DIG_IDCODE_LO
#define DPCSSYS_CR3_SUPX_DIG_IDCODE_LO__DATA__SHIFT                                                           0x0
//DPCSSYS_CR3_SUPX_DIG_IDCODE_HI
#define DPCSSYS_CR3_SUPX_DIG_IDCODE_HI__DATA__SHIFT                                                           0x0
//DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x0001L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x0004L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x01F0L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x0200L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x0400L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x0800L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x1000L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x2000L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x4000L
#define DPCSSYS_CR3_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x8000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x0002L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x0004L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x0078L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x0080L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x0100L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0xFC00L
//DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x0003L
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x00FCL
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x0700L
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x3800L
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x4000L
#define DPCSSYS_CR3_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x8000L
//DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x0004L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x0010L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x0040L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x0080L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x0100L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x0400L
#define DPCSSYS_CR3_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0xF800L
//DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x0070L
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x0080L
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x0700L
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0xF000L
//DPCSSYS_CR3_SUPX_DIG_DEBUG
#define DPCSSYS_CR3_SUPX_DIG_DEBUG__DTB_SEL__SHIFT                                                            0x0
#define DPCSSYS_CR3_SUPX_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                    0x3
#define DPCSSYS_CR3_SUPX_DIG_DEBUG__RESERVED_15_4__SHIFT                                                      0x4
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_SUPX_DIG_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x0001L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x0002L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x0004L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x0008L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x0010L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x0020L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x0040L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x0080L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x0100L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x0200L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x0400L
#define DPCSSYS_CR3_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0xF800L
//DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x0038L
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x01C0L
#define DPCSSYS_CR3_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0xFE00L
//DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                        0x0
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                         0x1
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                   0x2
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                    0x3
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                        0x4
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                          0x6
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                        0x0
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                   0x1
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                   0x3
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                   0x4
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                   0x6
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_BG1
#define DPCSSYS_CR3_SUPX_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUPX_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
#define DPCSSYS_CR3_SUPX_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                     0x5
#define DPCSSYS_CR3_SUPX_ANA_BG1__RT_VREF_SEL__SHIFT                                                          0x7
#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR3_SUPX_ANA_BG1__NC4_MASK                                                                    0x0010L
#define DPCSSYS_CR3_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR3_SUPX_ANA_BG2
#define DPCSSYS_CR3_SUPX_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                        0x0
#define DPCSSYS_CR3_SUPX_ANA_BG2__SUP_CHOP_EN__SHIFT                                                          0x1
#define DPCSSYS_CR3_SUPX_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                        0x2
#define DPCSSYS_CR3_SUPX_ANA_BG2__VPHUD_SELREF__SHIFT                                                         0x3
#define DPCSSYS_CR3_SUPX_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                      0x4
#define DPCSSYS_CR3_SUPX_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                      0x5
#define DPCSSYS_CR3_SUPX_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                0x6
#define DPCSSYS_CR3_SUPX_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR3_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                               0x0
#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                  0x7
#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR3_SUPX_ANA_BG3
#define DPCSSYS_CR3_SUPX_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                               0x0
#define DPCSSYS_CR3_SUPX_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                  0x2
#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR3_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x00F0L
#define DPCSSYS_CR3_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x0200L
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x01FFL
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x00FFL
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x0100L
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x001FL
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x0020L
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x0001L
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x0002L
#define DPCSSYS_CR3_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                     0x1
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                      0x2
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                         0x3
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                        0x5
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                      0xf
//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x0002L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x0004L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x0038L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x0C00L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x003FL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x003FL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0xFFC0L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x000FL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x00F0L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x0F00L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0xF000L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x000FL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x01F0L
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0xFE00L
//DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x000FL
#define DPCSSYS_CR3_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x0100L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x0200L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x0100L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x0200L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x0001L
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x0006L
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x3FF0L
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR3_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_SUPX_DIG_ANA_STAT
#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x0001L
#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR3_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0xFFFCL
//DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x0002L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x0004L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x0010L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x0020L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x0040L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x0300L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR3_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA
#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR3_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR3_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR3_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR3_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR3_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR3_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR3_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR3_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR3_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_ATB1
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_ATB2
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR3_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_MISC1
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_MISC2
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_MISC3
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR3_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_CLK_1
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_CLK_2
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR3_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL
#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_SQ
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR3_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_CAL1
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_CAL2
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1
#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR3_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR3_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR3_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L


// addressBlock: dpcssys_cr4_rdpcstxcrind
//DPCSSYS_CR4_SUP_DIG_IDCODE_LO
#define DPCSSYS_CR4_SUP_DIG_IDCODE_LO__DATA__SHIFT                                                            0x0
//DPCSSYS_CR4_SUP_DIG_IDCODE_HI
#define DPCSSYS_CR4_SUP_DIG_IDCODE_HI__DATA__SHIFT                                                            0x0
//DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                                0x2
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                              0x4
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                      0x9
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                      0xa
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                              0xb
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                                0xc
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                    0xd
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                            0xe
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                   0x0001L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                  0x0004L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                                0x01F0L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                        0x0200L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                        0x0400L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                                0x0800L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                  0x1000L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                      0x2000L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                              0x4000L
#define DPCSSYS_CR4_SUP_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                 0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                             0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                       0xd
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                    0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                            0xf
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                     0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                   0x00C0L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                               0x0100L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0600L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0800L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                               0x1000L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                         0x2000L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                      0x4000L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                              0x8000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                               0x0008L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                              0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                                0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                        0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                               0x001FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                          0xFFE0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                            0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                             0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                             0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                               0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                       0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                                0xf
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                         0x7F00L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                  0x8000L
//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                     0x1
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                 0x2
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                   0x3
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                                0x7
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                       0x8
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                    0x9
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                       0x0002L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                   0x0004L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                     0x0078L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                  0x0080L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                         0x0100L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                      0x0200L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                  0xFC00L
//DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                               0x0
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                            0x2
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                       0x8
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                       0xb
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                       0xe
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                           0xf
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                 0x0003L
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                              0x00FCL
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                         0x0700L
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                         0x3800L
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                         0x4000L
#define DPCSSYS_CR4_SUP_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                             0x8000L
//DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x2
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x3
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x4
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                                0x6
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0x7
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0x9
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                  0xa
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                               0xb
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                              0x0002L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                    0x0004L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                            0x0008L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                    0x0010L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                  0x0040L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                          0x0080L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                   0x0100L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                           0x0200L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                    0x0400L
#define DPCSSYS_CR4_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                 0xF800L
//DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x4
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                              0x7
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                       0x8
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                    0xb
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                   0x0070L
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                                0x0080L
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                         0x0700L
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                      0x0800L
#define DPCSSYS_CR4_SUP_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR4_SUP_DIG_DEBUG
#define DPCSSYS_CR4_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define DPCSSYS_CR4_SUP_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                     0x3
#define DPCSSYS_CR4_SUP_DIG_DEBUG__RESERVED_15_4__SHIFT                                                       0x4
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                    0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                 0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                             0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                            0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                           0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                            0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                    0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                            0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                   0x0060L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                               0x0080L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                              0x0300L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                             0x0400L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                              0x0800L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                            0x0FFFL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                              0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                       0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                        0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                 0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                            0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                             0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                                0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                         0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                          0x0008L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                   0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                              0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                               0xFFC0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                       0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                         0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                        0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                   0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                     0xFFFFL
//DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                  0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                             0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                    0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                               0xFFF0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                  0x01FEL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                           0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                     0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                             0x0003L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                       0x001CL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                        0xFFE0L
//DPCSSYS_CR4_SUP_DIG_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET__SHIFT                                                         0x0
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                        0x1
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                       0x2
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                       0x3
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                    0x4
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                         0x5
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                         0x6
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                       0x7
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                       0x8
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                                0x9
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                                0xa
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                    0xb
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__PHY_RESET_MASK                                                           0x0001L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_CLK_EN_MASK                                                          0x0002L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_USE_PAD_MASK                                                         0x0004L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_BURNIN_MASK                                                         0x0008L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                      0x0010L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_REQ_MASK                                                           0x0020L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RTUNE_ACK_MASK                                                           0x0040L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLA_STATE_MASK                                                         0x0080L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__MPLLB_STATE_MASK                                                         0x0100L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                  0x0200L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                  0x0400L
#define DPCSSYS_CR4_SUP_DIG_ASIC_IN__RESERVED_15_11_MASK                                                      0xF800L
//DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x3
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                           0x6
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                 0x9
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                    0x0007L
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                   0x0038L
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                             0x01C0L
#define DPCSSYS_CR4_SUP_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                   0xFE00L
//DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR4_SUP_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                               0xFFFEL
//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                            0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                             0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                           0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                              0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                               0x3F80L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                             0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                       0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                        0x007FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                         0x3F80L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                         0x0
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                          0x1
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                    0x2
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                     0x3
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                         0x4
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                           0x6
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_SUP_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                         0x0
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                    0x2
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                    0x3
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                    0x4
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                    0x5
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                    0x6
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_BG1
#define DPCSSYS_CR4_SUP_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                      0x0
#define DPCSSYS_CR4_SUP_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                    0x2
#define DPCSSYS_CR4_SUP_ANA_BG1__NC4__SHIFT                                                                   0x4
#define DPCSSYS_CR4_SUP_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                      0x5
#define DPCSSYS_CR4_SUP_ANA_BG1__RT_VREF_SEL__SHIFT                                                           0x7
#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR4_SUP_ANA_BG1__NC4_MASK                                                                     0x0010L
#define DPCSSYS_CR4_SUP_ANA_BG1__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR4_SUP_ANA_BG2
#define DPCSSYS_CR4_SUP_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                         0x0
#define DPCSSYS_CR4_SUP_ANA_BG2__SUP_CHOP_EN__SHIFT                                                           0x1
#define DPCSSYS_CR4_SUP_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                         0x2
#define DPCSSYS_CR4_SUP_ANA_BG2__VPHUD_SELREF__SHIFT                                                          0x3
#define DPCSSYS_CR4_SUP_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                       0x4
#define DPCSSYS_CR4_SUP_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                       0x5
#define DPCSSYS_CR4_SUP_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                 0x6
#define DPCSSYS_CR4_SUP_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                       0x7
#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR4_SUP_ANA_BG2__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                                0x0
#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                   0x7
#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_SUP_ANA_BG3
#define DPCSSYS_CR4_SUP_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                                0x0
#define DPCSSYS_CR4_SUP_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4__SHIFT                                                                 0x4
#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8__SHIFT                                                         0x8
#define DPCSSYS_CR4_SUP_ANA_BG3__NC7_4_MASK                                                                   0x00F0L
#define DPCSSYS_CR4_SUP_ANA_BG3__RESERVED_15_8_MASK                                                           0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                             0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                 0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                        0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                                0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                                0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                                0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                     0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                                0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                 0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                                0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                    0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                    0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                     0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                       0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                        0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                 0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                     0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                      0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                     0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                               0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                 0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                     0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                                0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                    0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                   0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                      0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                                0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                               0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                  0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                               0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                 0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                         0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                         0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                        0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                               0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                              0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                        0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                       0x2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                  0x3
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                     0x4
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                       0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                          0x1
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                         0x6
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                  0x7
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR4_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                             0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                              0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                               0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                     0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                     0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                       0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                               0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                                0x0008L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                 0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                        0x03E0L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                       0x0400L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                       0xF800L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                           0x000FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                        0x0010L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                        0x0020L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                        0x0040L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                       0x0100L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                            0x0200L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                            0x0400L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                         0x0800L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                           0x1000L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                               0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                       0xa
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                              0x001FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                 0x03E0L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                         0xFC00L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                           0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                        0xe
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                             0x3F00L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                          0xC000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                                0x8
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                  0xFF00L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT                0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                   0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                 0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                  0x003FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                   0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT                0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                   0x6
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT               0xc
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                  0x003FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                     0x0FC0L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                 0xF000L
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                        0x0001L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                      0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                         0x5
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                        0x001FL
#define DPCSSYS_CR4_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                           0xFFE0L
//DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                       0x0003L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_SUP_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                      0x01FFL
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                        0x0200L
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                               0x8
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                 0x0100L
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                           0x001FL
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                      0x0020L
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                  0x0
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                      0x1
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                    0x0001L
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                        0x0002L
#define DPCSSYS_CR4_SUP_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG
#define DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define DPCSSYS_CR4_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                   0x1
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                                0x6
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                     0x0002L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                      0x0004L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                              0x0038L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                  0xFFC0L
//DPCSSYS_CR4_SUP_DIG_RTUNE_STAT
#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                      0xa
#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                 0xc
#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__STAT_MASK                                                             0x03FFL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                        0x0C00L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                   0xF000L
//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                 0x003FL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                             0x03FFL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                           0xFC00L
//DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                       0x003FL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                   0x03FFL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                              0xFC00L
//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                          0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                            0x4
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                             0x8
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                             0xc
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                            0x000FL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                              0x00F0L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                               0x0F00L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                               0xF000L
//DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                     0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                           0x4
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                           0x9
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                       0x000FL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                             0x01F0L
#define DPCSSYS_CR4_SUP_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                             0xFE00L
//DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                     0x000FL
#define DPCSSYS_CR4_SUP_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                            0x8
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                            0x9
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                              0x0100L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                              0x0200L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                 0x4
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                    0x5
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                    0x6
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                         0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                            0x8
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                            0x9
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                   0xd
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                        0xe
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                             0xf
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                      0x0001L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                   0x0010L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                      0x0020L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                      0x0040L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                           0x0080L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                              0x0100L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                              0x0200L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                     0x2000L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                          0x4000L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                               0x8000L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                        0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                          0x03FFL
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                        0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                         0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                          0x007FL
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                           0x3F80L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                         0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                            0x4
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                          0xe
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                           0x0001L
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                               0x0006L
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                              0x3FF0L
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                            0x4000L
#define DPCSSYS_CR4_SUP_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_SUP_DIG_ANA_STAT
#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                               0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                            0x1
#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                    0x2
#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                 0x0001L
#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                              0x0002L
#define DPCSSYS_CR4_SUP_DIG_ANA_STAT__RESERVED_15_2_MASK                                                      0xFFFCL
//DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                             0x1
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                             0x2
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                                0x3
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                             0x4
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                     0x5
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                       0x6
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                          0x8
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                  0xa
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                            0xb
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                       0x0001L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                               0x0002L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                               0x0004L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                  0x0008L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                               0x0010L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                       0x0020L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                         0x0040L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                            0x0300L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                    0x0400L
#define DPCSSYS_CR4_SUP_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                              0xF800L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                    0x0
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                             0x8
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                      0x003FL
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                               0x0100L
#define DPCSSYS_CR4_SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_LANE0_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR4_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR4_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR4_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR4_LANE0_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE0_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_ATB1
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_ATB2
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR4_LANE0_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_MISC1
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_MISC2
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_MISC3
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR4_LANE0_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE0_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA
#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR4_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR4_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR4_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR4_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR4_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR4_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR4_LANE1_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR4_LANE1_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE1_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_ATB1
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_ATB2
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR4_LANE1_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_MISC1
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_MISC2
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_MISC3
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR4_LANE1_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE1_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_CLK_1
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_CLK_2
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR4_LANE1_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL
#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_SQ
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR4_LANE1_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_CAL1
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_CAL2
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1
#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE1_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA
#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR4_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR4_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR4_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR4_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR4_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR4_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR4_LANE2_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR4_LANE2_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE2_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_ATB1
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_ATB2
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR4_LANE2_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_MISC1
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_MISC2
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_MISC3
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR4_LANE2_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE2_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_CLK_1
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_CLK_2
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR4_LANE2_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL
#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_SQ
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR4_LANE2_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_CAL1
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_CAL2
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1
#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE2_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_LANE3_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR4_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR4_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR4_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR4_LANE3_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANE3_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_ATB1
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_ATB2
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR4_LANE3_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_MISC1
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_MISC2
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_MISC3
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR4_LANE3_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANE3_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST_MASK                                                     0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL__RESERVED_15_1_MASK                                                    0xFFFEL
//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__MPLLA_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_BW_OVRD_IN__MPLLA_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__MPLLA_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL__SHIFT                              0x6
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL__SHIFT                               0x8
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN__SHIFT                                         0xa
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_WORD_DIV2_EN_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_VAL_MASK                                  0x001CL
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_TX_CLK_DIV_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_VAL_MASK                                0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV10_CLK_EN_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_VAL_MASK                                 0x0100L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_DIV8_CLK_EN_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__MPLLB_BW_OVRD_EN_MASK                                           0x0400L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_OVRD_IN__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_BW_OVRD_IN__MPLLB_BW_OVRD_VAL_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN__SHIFT                      0x7
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10__SHIFT                                 0xa
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_RANGE_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_VAL_MASK                       0x0070L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_CLK_SEL_OVRD_EN_MASK                        0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__MPLLB_SSC_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0__RESERVED_15_10_MASK                                   0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND
#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__DATA__SHIFT                                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWCMN_DIG_LANE_FSM_OP_XTND__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__MPLLA_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_VAL_MASK                        0x07FFL
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__MPLLB_FRACN_CTRL_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1__RESERVED_15_12_MASK                                   0xF000L
//DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL__SHIFT                                           0x4
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0x5
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL__SHIFT                                     0x6
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL__SHIFT                                       0xb
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN__SHIFT                                        0xc
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_VAL_MASK                                             0x0010L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN_MASK                                              0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_VAL_MASK                                       0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN_MASK                                        0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_VAL_MASK                                        0x0300L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_SEL_OVRD_EN_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_VAL_MASK                                         0x0800L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__TX_PWM_CLK_EN_OVRD_EN_MASK                                          0x1000L
#define DPCSSYS_CR4_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13_MASK                                                 0xE000L
//DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE__SHIFT                                             0x6
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE__SHIFT                                             0x7
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME__SHIFT                                      0x9
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL__SHIFT                                          0xd
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL__SHIFT                                          0xe
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15__SHIFT                                          0xf
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_OFF_TIME_MASK                                             0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_STATE_MASK                                               0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_STATE_MASK                                               0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_STATE_OVRD_OUT_EN_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLL_FORCE_ON_TIME_MASK                                        0x1E00L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLB_BANK_SEL_MASK                                            0x2000L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__MPLLA_BANK_SEL_MASK                                            0x4000L
#define DPCSSYS_CR4_RAWCMN_DIG_MPLL_STATE_CTL__RESERVED_15_15_MASK                                            0x8000L
//DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE
#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__DATA__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4__SHIFT                                              0x4
#define DPCSSYS_CR4_RAWCMN_DIG_TX_CAL_CODE__RESERVED_15_4_MASK                                                0xFFF0L
//DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE
#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__DATA__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR4_RAWCMN_DIG_SRAM_INIT_DONE__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR4_RAWCMN_DIG_OCLA
#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2__SHIFT                                                     0x2
#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__DIV2_CLK_EN_MASK                                                         0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__TCA_OCLA_PROBE_SEL_MASK                                                  0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_OCLA__RESERVED_15_2_MASK                                                       0xFFFCL
//DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                0x0
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                               0x1
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN__SHIFT                               0x4
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL__SHIFT                              0x5
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__REF_ALT_CLK_LP_SEL_OVRD_VAL_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_PRE_HP_OVRD_VAL_MASK                                         0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_EN_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__SUP_RX_VCO_VREF_SEL_OVRD_VAL_MASK                                0x00E0L
#define DPCSSYS_CR4_RAWCMN_DIG_SUP_ANA_OVRD__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE
#define DPCSSYS_CR4_RAWCMN_DIG_PCS_RAW_ID_CODE__DATA__SHIFT                                                   0x0
//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1
#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_1__W_ID_CODE_1_MASK                                                 0xFFFFL
//DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2
#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWCMN_DIG_FW_ID_CODE_2__W_ID_CODE_2_MASK                                                 0xFFFFL
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RTUNE_TXUP_VAL_0_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_0__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_1__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RTUNE_TXUP_VAL_1_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_1__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_2__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RTUNE_TXUP_VAL_2_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_3__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RTUNE_TXUP_VAL_3_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_4__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RTUNE_TXUP_VAL_4_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_4__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_5__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RTUNE_TXUP_VAL_5_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_5__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_6__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RTUNE_TXUP_VAL_6_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_6__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7_MASK                                    0x003FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_7__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7__SHIFT                              0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RTUNE_TXUP_VAL_7_MASK                                0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_7__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM__SHIFT                                        0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_PGATE_BL_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_ROM_MASK                                          0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_BYPASS_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__SRAM_BL_START_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SRAM_BL_CFG__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PMA_PWR_STABLE_OVRD_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PCS_PWR_STABLE_OVRD_MASK                                   0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_VAL_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_RESET_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__PG_MODE_EN_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_IN__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN__SHIFT                                   0x4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PMA_PWR_EN_OVRD_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__PCS_PWR_EN_OVRD_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_VAL_MASK                                0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_VALID_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__MON_IN_PULL_DOWN_MASK                                     0x0010L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_PG_OVRD_OUT__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                            0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                             0x3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                0x4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                           0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                            0x7
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                           0x8
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL_MASK                              0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN_MASK                               0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_VAL_MASK                             0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLA_FORCE_ACK_OVRD_EN_MASK                              0x0080L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_VAL_MASK                             0x0100L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__MPLLB_FORCE_ACK_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_SUP_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH__SHIFT                                0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__SUP_ANA_VPHUD_SELVPH_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__VREF_CAL_DONE_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_VREF_STATS__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN__SHIFT                                         0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT__SHIFT                                        0x3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT__SHIFT                                        0x5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_IN_MASK                                           0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_IN_MASK                                           0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_OVRD_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_MASK                                          0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_REQ_OUT_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_MASK                                          0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RES_ACK_OUT_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_OVRD_IN__RESERVED_15_7_MASK                                        0xFF80L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_IN_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_REQ_OUT_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_IN_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RES_ACK_OUT_MASK                                      0x0008L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_RES_ASIC_IN_OUT__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_VAL_MASK                                          0x001FL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_REF_RANGE_OVRD__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__MPLL_PWRDN_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR4_RAWCMN_DIG_AON_CMN_MISC_CONF_IN_1__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR4_RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR4_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR4_RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR4_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR4_RAWLANE2_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR4_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR4_RAWLANE3_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR4_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_STATS
#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWAONLANE0_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR4_RAWAONLANE0_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_STATS
#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWAONLANE1_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR4_RAWAONLANE1_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_STATS
#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWAONLANE2_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR4_RAWAONLANE2_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_STATS
#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWAONLANE3_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR4_RAWAONLANE3_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_ATT_IDAC_OFST__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_AFE_CTLE_IDAC_OFST__RESERVED_15_8_MASK                                    0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7__SHIFT                                          0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__IQ_ADPT_VAL_MASK                                              0x007FL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_IQ__RESERVED_15_7_MASK                                            0xFF80L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__DATA__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_FOM__RESERVED_15_8_MASK                                          0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_SUMMER_ODD_IDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_EVEN_REF_LVL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ODD_REF_LVL__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_LIN__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_PHSADJ_MAP__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__DATA__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__DATA__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__DATA__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__DATA__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                           0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8_MASK                             0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__DATA__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                            0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                              0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__DATA__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                             0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                               0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__DATA__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                    0xFF80L
//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLA_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8__SHIFT                                   0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLLB_COARSE_TUNE__RESERVED_15_8_MASK                                     0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__PH2_PWRUP_DONE_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_INIT_PWRUP_DONE__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__ATT_ADPT_VAL_MASK                                            0x00FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_ATT__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__VGA_ADPT_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_VGA__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_BOOST_ADPT_VAL_MASK                                    0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__CTLE_POLE_ADPT_VAL_MASK                                     0x1C00L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_CTLE__RESERVED_15_13_MASK                                         0xE000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__DFE_TAP1_ADPT_VAL_MASK                                  0x1FFFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADAPT_DONE__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                          0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL__SHIFT                                        0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL__SHIFT                                         0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP__SHIFT                                               0x9
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET__SHIFT                                          0xb
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                        0xe
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_STARTUP_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_ADAPT_MASK                                            0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_CAL_MASK                                          0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_CAL_MASK                                          0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_BYPASS_CAL_MASK                                       0x0010L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_REFLVL_CAL_MASK                                       0x0020L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_IQ_CAL_MASK                                           0x0040L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_AFE_ADAPT_MASK                                        0x0080L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_DFE_ADAPT_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_SUP_MASK                                                 0x0200L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_CMN_MODE_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_TX_RXDET_MASK                                            0x0800L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_PWRUP_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_WAIT_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__FAST_RX_VCO_CAL_MASK                                          0x4000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__DFE_TAP2_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP2__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__DFE_TAP3_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP3__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__DFE_TAP4_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP4__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__DFE_TAP5_ADPT_VAL_MASK                                  0x0FFFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_ADPT_DFE_TAP5__RESERVED_15_12_MASK                                     0xF000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                            0x000FL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                                  0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                             0x000FL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                                    0xFFF0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__LANE_CMNCAL_MPLL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_0__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_1__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_2__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_3__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_4__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_5__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_6__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_ADPT_CTL_7__VAL_MASK                                                      0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2__SHIFT                                        0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLA_DISABLE_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__LANE_MPLLB_DISABLE_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_DISABLE__RESERVED_15_2_MASK                                          0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL__SHIFT                                0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL__SHIFT                               0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL__SHIFT                                 0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL__SHIFT                               0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL__SHIFT                                0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL__SHIFT                                      0x9
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL__SHIFT                                      0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL__SHIFT                                   0xe
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_CAL_ADAPT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_ADAPT_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DATA_CAL_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_PHASE_CAL_MASK                                 0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_AFE_CAL_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_CONT_DCC_CAL_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_DCC_CAL_MASK                                   0x0040L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VPHUD_CAL_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_CONT_VREF_CAL_MASK                                  0x0100L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_TX_DCC_CAL_MASK                                        0x0200L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_DCC_CAL_MASK                                        0x0400L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VPHUD_CAL_MASK                                      0x0800L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_VREF_CAL_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__SKIP_TX_RTUNE_CAL_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__FAST_RX_SIGDET_CAL_MASK                                     0x4000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FAST_FLAGS_2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT__SHIFT                     0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_INIT_MASK                       0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__LANE_CMNCAL_RCAL_DONE_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_VAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RX_DISABLE_OVRD_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__TX_DISABLE_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TXRX_OVRD_IN__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                     0x01FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF__SHIFT                             0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS__SHIFT                     0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN__SHIFT                      0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__ISOLATE_SIGDET_HF_MASK                               0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_DIS_MASK                       0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDEF_HF_FILT_OVR_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RX_SIGDET_LF_OUT_FILT_EN_MASK                        0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_FILT_CTRL__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_STATS
#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER__SHIFT                                           0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT__SHIFT                                               0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2__SHIFT                                               0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_VREFGEN_MASTER_MASK                                             0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RX_PMA_SQ_OUT_MASK                                                 0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_STATS__RESERVED_15_2_MASK                                                 0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                        0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL__SHIFT                         0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL__SHIFT                     0x9
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN__SHIFT                      0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL__SHIFT                               0xb
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN__SHIFT                                0xc
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13__SHIFT                                      0xd
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_VAL_MASK                         0x0007L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_TRESH_OVRD_EN_MASK                          0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_VAL_MASK                          0x0030L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_CTRL_RESP_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_VAL_MASK                           0x0080L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_WEAKKEEP_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_VAL_MASK                       0x0200L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_INV_POLARITY_OVRD_EN_MASK                        0x0400L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_VAL_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RX_PMA_SQ_EN_OVRD_EN_MASK                                  0x1000L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_1__RESERVED_15_13_MASK                                        0xE000L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL__SHIFT                                  0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL__SHIFT                           0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL__SHIFT                             0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_VAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_VREFGEN_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_VAL_MASK                                    0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_SQ_OUT_OVRD_EN_MASK                                     0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_VAL_MASK                             0x0010L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_ACDC_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_VAL_MASK                               0x0040L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RX_PMA_TERM_EN_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_2__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL__SHIFT                 0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                  0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL__SHIFT                        0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN__SHIFT                         0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6__SHIFT                                       0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_VAL_MASK                   0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                    0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_VAL_MASK                          0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_LF_EN_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_VAL_MASK                          0x0010L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RX_PMA_SIGDET_HF_EN_OVRD_EN_MASK                           0x0020L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_OVRD_OUT_3__RESERVED_15_6_MASK                                         0xFFC0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD__SHIFT                          0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN__SHIFT                                0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7__SHIFT                                       0x7
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_LF_THRESHOLD_MASK                            0x0007L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_HF_THRESHOLD_MASK                            0x0038L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RX_PMA_SIGDET_CAL_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CAL__RESERVED_15_7_MASK                                         0xFF80L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RX_PMA_SIGDET_HF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_HF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RX_PMA_SIGDET_LF_CAL_TUNE_MASK                         0x003FL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_LF_CODE__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__PULL_UP_MASK                                               0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_VREFGEN_EN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__DATA__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_IOFF_CODE__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__DATA__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_ICONST_CODE__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_CAL_VREFGEN_CODE__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_0__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RX_DCC_CAL_ICM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_ICM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RX_DCC_CAL_IDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_IDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RX_DCC_CAL_QCM_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QCM_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10__SHIFT                              0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RX_DCC_CAL_QDF_CODE_MASK                           0x03FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_DCC_CAL_QDF_CODE_1__RESERVED_15_10_MASK                                0xFC00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_BANK_DATA__DATA_MASK                                               0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONT__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_WAIT_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__MPLL_STATE_DLY_EN_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_MPLL_BG_CTL__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN__SHIFT                          0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                         0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                           0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_HF_OUT_OVRD_EN_MASK                            0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                           0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RX_SIGDET_LF_OUT_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_OVRD__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL__SHIFT                           0x1
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2__SHIFT                                       0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_HF_OUT_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RX_SIGDET_LF_OUT_OVRD_VAL_MASK                             0x0002L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_SIGDET_OUT_IN__RESERVED_15_2_MASK                                         0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_MM_CONFIG__DATA__SHIFT                                                 0x0
//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__REF_LVL_ADPT_MASK                                         0x00FFL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_ADPT_CONFIG__FW_CONFIG_MASK                                            0xFF00L
//DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_FW_CALIB_CONFIG__FW_CALIB_MASK                                            0xFFFFL
//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                     0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                              0x3
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_VAL_MASK                      0x0003L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN_MASK                       0x0004L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3_MASK                                0xFFF8L
//DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__LANE_XCVR_MODE_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_LANE_XCVR_MODE_IN__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER__SHIFT                      0x0
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER__SHIFT                      0x5
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD__SHIFT                                0xa
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_HF_FILTER_COUNTER_MASK                        0x001FL
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_FILTER_COUNTER_MASK                        0x03E0L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RX_SIGDET_LF_HOLD_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWAONLANEX_DIG_RX_SIGDET_CONFIG__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG
#define DPCSSYS_CR4_RAWAONLANEX_DIG_TX_DCC_CONFIG__DATA__SHIFT                                                0x0
//DPCSSYS_CR4_SUPX_DIG_IDCODE_LO
#define DPCSSYS_CR4_SUPX_DIG_IDCODE_LO__DATA__SHIFT                                                           0x0
//DPCSSYS_CR4_SUPX_DIG_IDCODE_HI
#define DPCSSYS_CR4_SUPX_DIG_IDCODE_HI__DATA__SHIFT                                                           0x0
//DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT                                                0x0
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT                                               0x2
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT                                             0x4
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT                                     0x9
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT                                                     0xa
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT                                             0xb
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT                                               0xc
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                   0xd
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD__SHIFT                                           0xe
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN__SHIFT                                        0xf
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_MASK                                                  0x0001L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_MASK                                                 0x0004L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_MASK                                               0x01F0L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN_MASK                                       0x0200L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_MASK                                                       0x0400L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN_MASK                                               0x0800L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_EN_MASK                                                 0x1000L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN_MASK                                     0x2000L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_MASK                                             0x4000L
#define DPCSSYS_CR4_SUPX_DIG_REFCLK_OVRD_IN__SUP_PRE_HP_OVRD_EN_MASK                                          0x8000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__MPLLA_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                  0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN_MASK                                    0x0200L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6__SHIFT                                     0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__MPLLB_HDMI_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_OVRD_IN__RESERVED_15_6_MASK                                       0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I__SHIFT                                                0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__MPLLA_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_1__MPLLA_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__MPLLA_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_1__MPLLA_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__MPLLA_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_3__MPLLA_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_4__MPLLA_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_OVRD_IN_5__MPLLA_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_OVRD_IN__MPLLA_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN__SHIFT                                                  0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I__SHIFT                                                0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN__SHIFT                                            0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD__SHIFT                                      0xd
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN__SHIFT                                   0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15__SHIFT                                           0xf
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__OVRD_EN_MASK                                                    0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_V2I_MASK                                                  0x00C0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_STANDBY_MASK                                              0x0100L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0600L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0800L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLL_FRACN_EN_MASK                                              0x1000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_MASK                                        0x2000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__MPLLB_CLK_SYNC_OVRD_EN_MASK                                     0x4000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_0__RESERVED_15_15_MASK                                             0x8000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_OVRD_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_PMIX_EN_MASK                                              0x0008L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_1__MPLLB_SSC_PEAK_15_0_MASK                                       0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4__SHIFT                                           0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__MPLLB_SSC_PEAK_19_16_MASK                                      0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_PEAK_2__RESERVED_15_4_MASK                                             0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0__SHIFT                             0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_1__MPLLB_SSC_STEPSIZE_15_0_MASK                               0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__MPLLB_SSC_STEPSIZE_20_16_MASK                              0x001FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_STEPSIZE_2__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_3__MPLLB_FRACN_QUOT_MASK                                           0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_4__MPLLB_FRACN_REM_MASK                                            0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_OVRD_IN_5__MPLLB_FRACN_DEN_MASK                                            0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_OVRD_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN__SHIFT                              0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS__SHIFT                                      0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN__SHIFT                               0xf
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_PROP_GS_OVR_EN_MASK                                0x0080L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_MASK                                        0x7F00L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_OVRD_IN__MPLLB_CP_INT_GS_OVR_EN_MASK                                 0x8000L
//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE__SHIFT                                                  0x3
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN__SHIFT                                               0x7
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD__SHIFT                                      0x8
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                                   0x9
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10__SHIFT                                               0xa
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__PRESCALER_OVRD_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_REQ_MASK                                                      0x0002L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RTUNE_OVRD_EN_MASK                                                  0x0004L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_MASK                                                    0x0078L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__TX_CAL_CODE_EN_MASK                                                 0x0080L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_MASK                                        0x0100L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN_MASK                                     0x0200L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_IN__RESERVED_15_10_MASK                                                 0xFC00L
//DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE__SHIFT                                              0x0
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE__SHIFT                                           0x2
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV__SHIFT                                      0x8
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV__SHIFT                                      0xb
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT__SHIFT                                      0xe
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN__SHIFT                                          0xf
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_RANGE_MASK                                                0x0003L
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__DCO_FINETUNE_MASK                                             0x00FCL
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLB_DIV_MASK                                        0x0700L
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLK_MPLLA_DIV_MASK                                        0x3800L
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_RESULT_MASK                                        0x4000L
#define DPCSSYS_CR4_SUPX_DIG_PRESCALER_OVRD_IN__REF_CLKDET_EN_MASK                                            0x8000L
//DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                 0x2
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                 0x4
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE__SHIFT                                               0x6
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                       0x7
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE__SHIFT                                                0x8
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK__SHIFT                                                 0xa
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11__SHIFT                                              0xb
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_MASK                                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_MASK                                                   0x0004L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_MASK                                                   0x0010L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_MASK                                                 0x0040L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN_MASK                                         0x0080L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_MASK                                                  0x0100L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__REF_CLK_ACK_MASK                                                   0x0400L
#define DPCSSYS_CR4_SUPX_DIG_SUP_OVRD_OUT__RESERVED_15_11_MASK                                                0xF800L
//DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                0x4
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN__SHIFT                                             0x7
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR__SHIFT                                      0x8
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12__SHIFT                                               0xc
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RX_VREF_CTRL_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_MASK                                                  0x0070L
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_EN_MASK                                               0x0080L
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_MASK                                        0x0700L
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__SUP_RX_VCO_VREF_SEL_OVR_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_SUPX_DIG_LVL_OVRD_IN__RESERVED_15_12_MASK                                                 0xF000L
//DPCSSYS_CR4_SUPX_DIG_DEBUG
#define DPCSSYS_CR4_SUPX_DIG_DEBUG__DTB_SEL__SHIFT                                                            0x0
#define DPCSSYS_CR4_SUPX_DIG_DEBUG__REF_DCO_CLK_SEL__SHIFT                                                    0x3
#define DPCSSYS_CR4_SUPX_DIG_DEBUG__RESERVED_15_4__SHIFT                                                      0x4
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I__SHIFT                                                0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_EN_MASK                                                   0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__MPLLA_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__MPLLA_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_3__MPLLA_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__MPLLA_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_5__MPLLA_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__MPLLA_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN__SHIFT                                        0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                         0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I__SHIFT                                                0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY__SHIFT                                            0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO__SHIFT                                           0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE__SHIFT                                          0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN__SHIFT                                           0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_EN_MASK                                                   0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_DIV5_CLK_EN_MASK                                          0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV_MASK                                           0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_V2I_MASK                                                  0x0060L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_STANDBY_MASK                                              0x0080L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FREQ_VCO_MASK                                             0x0300L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_CAL_FORCE_MASK                                            0x0400L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__MPLLB_FRACN_EN_MASK                                             0x0800L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_0__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                           0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER_MASK                                           0x0FFFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12_MASK                                             0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD__SHIFT                                      0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN__SHIFT                                            0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN__SHIFT                                0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC__SHIFT                                           0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6__SHIFT                                            0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_SSC_UP_SPREAD_MASK                                        0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_PMIX_EN_MASK                                              0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_WORD_DIV2_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_FRACN_CFG_UPDATE_EN_MASK                                  0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__MPLLB_CLK_SYNC_MASK                                             0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_2__RESERVED_15_6_MASK                                              0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                      0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_3__MPLLB_SSC_PEAK_15_0_MASK                                        0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__MPLLB_SSC_PEAK_19_16_MASK                                       0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_4__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0__SHIFT                                  0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_5__MPLLB_SSC_STEPSIZE_15_0_MASK                                    0xFFFFL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16__SHIFT                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4__SHIFT                                            0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__MPLLB_SSC_STEPSIZE_20_16_MASK                                   0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_ASIC_IN_6__RESERVED_15_4_MASK                                              0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__MPLLA_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                               0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER_MASK                                 0x01FEL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                          0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                    0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV_MASK                            0x0003L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__MPLLB_HDMI_DIV_MASK                                      0x001CL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_HDMI_CLK_ASIC_IN__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_SUPX_DIG_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET__SHIFT                                                        0x0
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN__SHIFT                                                       0x1
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD__SHIFT                                                      0x2
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN__SHIFT                                                      0x3
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN__SHIFT                                                   0x4
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ__SHIFT                                                        0x5
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK__SHIFT                                                        0x6
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE__SHIFT                                                      0x7
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE__SHIFT                                                      0x8
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN__SHIFT                                               0x9
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL__SHIFT                                               0xa
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11__SHIFT                                                   0xb
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__PHY_RESET_MASK                                                          0x0001L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_CLK_EN_MASK                                                         0x0002L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_USE_PAD_MASK                                                        0x0004L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_BURNIN_MASK                                                        0x0008L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_POWERDOWN_MASK                                                     0x0010L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_REQ_MASK                                                          0x0020L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RTUNE_ACK_MASK                                                          0x0040L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLA_STATE_MASK                                                        0x0080L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__MPLLB_STATE_MASK                                                        0x0100L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__TEST_TX_REF_CLK_EN_MASK                                                 0x0200L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__REF_ALT_CLK_LP_SEL_MASK                                                 0x0400L
#define DPCSSYS_CR4_SUPX_DIG_ASIC_IN__RESERVED_15_11_MASK                                                     0xF800L
//DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                0x3
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL__SHIFT                                          0x6
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9__SHIFT                                                0x9
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RX_VREF_CTRL_MASK                                                   0x0007L
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__TX_VBOOST_LVL_MASK                                                  0x0038L
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__SUP_RX_VCO_VREF_SEL_MASK                                            0x01C0L
#define DPCSSYS_CR4_SUPX_DIG_LVL_ASIC_IN__RESERVED_15_9_MASK                                                  0xFE00L
//DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_SUPX_DIG_BANDGAP_ASIC_IN__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__MPLLA_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__MPLLA_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP__SHIFT                                           0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT__SHIFT                                            0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14__SHIFT                                          0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_PROP_MASK                                             0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__MPLLB_CP_INT_MASK                                              0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_ASIC_IN__RESERVED_15_14_MASK                                            0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS__SHIFT                                      0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14__SHIFT                                       0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_PROP_GS_MASK                                       0x007FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__MPLLB_CP_INT_GS_MASK                                        0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_CP_GS_ASIC_IN__RESERVED_15_14_MASK                                         0xC000L
//DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__PSCALER_ATB_SELECT__SHIFT                                        0x0
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__PSCALER_MEAS_VREG__SHIFT                                         0x1
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__PSCALER_OVRD_FAST_START__SHIFT                                   0x2
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__PSCALER_FAST_START_REG__SHIFT                                    0x3
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__PSCALER_VREG_BOOST__SHIFT                                        0x4
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__PSCALER_HYST_REF__SHIFT                                          0x6
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_SUPX_ANA_PRESCALER_CTRL__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_ATB__SHIFT                                                        0x0
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBF__SHIFT                                                   0x1
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_SEL_ATBP__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_VP4O8_EN__SHIFT                                                   0x3
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_DAC_CHOP__SHIFT                                                   0x4
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_DAC_MODE__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RT_EN_FRCON__SHIFT                                                   0x6
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__PSCALER_VREG_FB_DIV_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_RTUNE_CTRL__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_BG1
#define DPCSSYS_CR4_SUPX_ANA_BG1__SUP_SEL_VBG_VREF__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUPX_ANA_BG1__SUP_SEL_VPHUD_VREF__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4__SHIFT                                                                  0x4
#define DPCSSYS_CR4_SUPX_ANA_BG1__SUP_SEL_VPLL_REF__SHIFT                                                     0x5
#define DPCSSYS_CR4_SUPX_ANA_BG1__RT_VREF_SEL__SHIFT                                                          0x7
#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR4_SUPX_ANA_BG1__NC4_MASK                                                                    0x0010L
#define DPCSSYS_CR4_SUPX_ANA_BG1__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR4_SUPX_ANA_BG2
#define DPCSSYS_CR4_SUPX_ANA_BG2__SUP_BYPASS_BG__SHIFT                                                        0x0
#define DPCSSYS_CR4_SUPX_ANA_BG2__SUP_CHOP_EN__SHIFT                                                          0x1
#define DPCSSYS_CR4_SUPX_ANA_BG2__SUP_TEMP_MEAS__SHIFT                                                        0x2
#define DPCSSYS_CR4_SUPX_ANA_BG2__VPHUD_SELREF__SHIFT                                                         0x3
#define DPCSSYS_CR4_SUPX_ANA_BG2__ATB_EXT_MEAS_EN__SHIFT                                                      0x4
#define DPCSSYS_CR4_SUPX_ANA_BG2__RT_TX_OFFSET_EN__SHIFT                                                      0x5
#define DPCSSYS_CR4_SUPX_ANA_BG2__SUP_SEL_TX_SWING_VREF__SHIFT                                                0x6
#define DPCSSYS_CR4_SUPX_ANA_BG2__PSCALER_VREG_OVERRIDE_RING_CTRL__SHIFT                                      0x7
#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR4_SUPX_ANA_BG2__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS
#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__SUP_ATB_SW__SHIFT                                               0x0
#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__SUP_TIE__SHIFT                                                  0x7
#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_ANA_SWITCH_PWR_MEAS__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR4_SUPX_ANA_BG3
#define DPCSSYS_CR4_SUPX_ANA_BG3__SUP_SEL_RX_VCO_TC_VREF__SHIFT                                               0x0
#define DPCSSYS_CR4_SUPX_ANA_BG3__SUP_SEL_RX_CAL_VREF__SHIFT                                                  0x2
#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4__SHIFT                                                                0x4
#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8__SHIFT                                                        0x8
#define DPCSSYS_CR4_SUPX_ANA_BG3__NC7_4_MASK                                                                  0x00F0L
#define DPCSSYS_CR4_SUPX_ANA_BG3__RESERVED_15_8_MASK                                                          0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLA_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__OVRD_GEAR_RC_FILT__SHIFT                                            0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__OVRD_TEST_RC_FILT__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__TEST_VREG_DIV__SHIFT                                                0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__VBG_EN__SHIFT                                                       0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__COUNT_SEL_LOCK__SHIFT                                               0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__PHASE_SEL_LOCK__SHIFT                                               0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC1__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__OVRD_PR_BYPASS__SHIFT                                               0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__PR_BYPASS__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__OVRD_GEARSHIFT__SHIFT                                               0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__GEARSHIFT_REG__SHIFT                                                0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__TEST_LOCK_GEAR__SHIFT                                               0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__EN_CAL_SPO__SHIFT                                                   0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__TEST_BOOST__SHIFT                                                   0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_MISC2__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__OVRD_ENABLE__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__ENABLE_REG__SHIFT                                                    0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__OVRD_CAL__SHIFT                                                      0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__CAL_REG__SHIFT                                                       0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__OVRD_FB_CLK_EN__SHIFT                                                0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__FB_CLK_EN_REG__SHIFT                                                 0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__OVRD_RESET__SHIFT                                                    0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESET_REG__SHIFT                                                     0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_OVRD__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__MEAS_IV_WRAP__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__ATB_SELECT__SHIFT                                                    0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__MEAS_IV_PLL__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__MEAS_IV_BIAS__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__CTR_UPLL_TUNNING__SHIFT                                              0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_ATB3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__CTR_ICP_INT__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__CTR_VREF_EN__SHIFT                                                   0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__CTR_VREF_VMARG__SHIFT                                                0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__CTR_CP_PLL__SHIFT                                                    0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR1__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__CTR_REGS_PLL__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR2__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__CTR_REGS_CP_PLL__SHIFT                                               0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__CTR_SPO_PLL__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__CTR_VINT_CAP__SHIFT                                                  0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR3__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__CTR_CP_8X__SHIFT                                                     0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__CTR_FIL_REG__SHIFT                                                   0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__CTR_CP_PROP_REF__SHIFT                                               0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__CTR_DOUBLER_GAIN__SHIFT                                              0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__CTR_TEST_CASC__SHIFT                                                 0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__CTR_RC_FITER__SHIFT                                                  0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR4__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_STANDBY_MODE__SHIFT                                              0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_LEG_SR_CON__SHIFT                                                0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_VREG_RING_OVERRIDE__SHIFT                                        0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_SPO_SPEED_OVERRIDE__SHIFT                                        0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_BYPASS_LOCK_SPO_CAL__SHIFT                                       0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_LOCK_SPO_CAL__SHIFT                                              0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__CTR_UPLL_RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8__SHIFT                                                 0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_CTR5__RESERVED_15_8_MASK                                                   0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_REF_FBK_BYPASS__SHIFT                                       0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_BYPASS_TX__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_BYPASS__SHIFT                                      0x2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_CLK_PMIX_BYPASS__SHIFT                                 0x3
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_RIGHT_BYPASS__SHIFT                                    0x4
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_VREG_LEFT_BYPASS__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__CTR_LEFT_RIGHT_GAIN__SHIFT                                      0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED1__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_MODE_90__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__CTR_DLL_RESERVED__SHIFT                                         0x1
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV24_DSQ_ENZ__SHIFT                                        0x6
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__CTR_DIV4__SHIFT                                                 0x7
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_ANA_MPLLB_RESERVED2__RESERVED_15_8_MASK                                              0xFF00L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLA_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN__SHIFT                                0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP__SHIFT                             0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK__SHIFT                              0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED__SHIFT                                    0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__OVRD_SEL_MASK                                      0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_FBDIGCLK_EN_MASK                              0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__MPLL_PCLK_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_PWRUP_MASK                               0x0008L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__FAST_MPLL_LOCK_MASK                                0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DTB_SEL_MASK                                       0x03E0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__DIV10_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD__RESERVED_MASK                                      0xF800L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                     0x4
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                     0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                   0x7
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                    0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                         0x9
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                         0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                      0xb
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                        0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__FSM_STATE_MASK                                          0x000FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_R_LANES_MASK                                       0x0010L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_L_LANES_MASK                                       0x0020L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN_MASK                                     0x0080L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN_MASK                                      0x0100L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_CAL_MASK                                           0x0200L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_RST_MASK                                           0x0400L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_ANA_EN_MASK                                        0x0800L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__MPLL_LOCK_MASK                                          0x1000L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE__SHIFT                           0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN__SHIFT                              0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10__SHIFT                      0xa
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__MAX_RANGE_MASK                             0x001FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__DAC_IN_MASK                                0x03E0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_DAC_MAXRANGE__RESERVED_15_10_MASK                        0xFC00L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME__SHIFT                          0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14__SHIFT                       0xe
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__LOCK_TIME_MASK                              0x00FFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__STABLE_TIME_MASK                            0x3F00L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_LOCK__RESERVED_15_14_MASK                         0xC000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME__SHIFT                               0x8
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__GEARSHIFT_TIME_MASK                              0x00FFL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS__PRESET_TIME_MASK                                 0xFF00L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME__SHIFT               0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME__SHIFT                  0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12__SHIFT                0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PWRDN_WAIT_TIME_MASK                 0x003FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__PCLK_EN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE__RESERVED_15_12_MASK                  0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME__SHIFT               0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME__SHIFT                  0x6
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12__SHIFT              0xc
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PCLK_DIS_TIME_MASK                 0x003FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__PWRDN_TIME_MASK                    0x0FC0L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_TIMERS_PCLK_STABLE_2__RESERVED_15_12_MASK                0xF000L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL__SHIFT                                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_MASK                                       0x0001L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__MPLL_CAL_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_CAL__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT__SHIFT                     0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5__SHIFT                        0x5
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__MPLL_ANA_DAC_OUT_MASK                       0x001FL
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_ANA_DAC_OUT__RESERVED_15_5_MASK                          0xFFE0L
//DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3__SHIFT                                  0x3
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__SPREAD_TYPE_MASK                                      0x0003L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__OVR_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_SUPX_DIG_MPLLB_SSC_GEN_SPREAD_TYPE__RESERVED_15_3_MASK                                    0xFFF8L
//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                     0x9
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME_MASK                                     0x01FFL
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT_MASK                                       0x0200L
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                  0x0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME_MASK                                    0x01FFL
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                            0x0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN__SHIFT                              0x8
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME_MASK                              0x00FFL
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_SUP_STATE_UPD_EN_MASK                                0x0100L
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                        0x0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                   0x5
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                   0x6
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME_MASK                          0x001FL
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT_MASK                                     0x0020L
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6_MASK                                     0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I__SHIFT                                 0x0
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I__SHIFT                                     0x1
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_SELVPH_I_MASK                                   0x0001L
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__SUP_ANA_VPHUD_EN_I_MASK                                       0x0002L
#define DPCSSYS_CR4_SUPX_DIG_CLK_RST_REF_VPHUD__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                     0x1
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                      0x2
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                         0x3
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                        0x5
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                      0xf
//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE__SHIFT                                                  0x1
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                           0x3
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RX_CAL_EN_MASK                                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__FAST_RTUNE_MASK                                                    0x0002L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__TX_CAL_EN_MASK                                                     0x0004L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL_MASK                                             0x0038L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT__SHIFT                                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE__SHIFT                                                     0xa
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12__SHIFT                                                0xc
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__STAT_MASK                                                            0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__DTB_RTUNE_MASK                                                       0x0C00L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_STAT__RESERVED_15_12_MASK                                                  0xF000L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                              0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                           0x6
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL_MASK                                                0x003FL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6_MASK                                             0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                          0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL_MASK                                            0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                              0x6
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RX_STAT_MASK                                                      0x003FL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_RX_STAT__RESERVED_15_6_MASK                                                0xFFC0L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__TXDN_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXDN_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                           0xa
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__TXUP_STAT_MASK                                                  0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TXUP_STAT__RESERVED_15_10_MASK                                             0xFC00L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME__SHIFT                                         0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME__SHIFT                                           0x4
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME__SHIFT                                            0x8
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME__SHIFT                                            0xc
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RESULT_TIME_MASK                                           0x000FL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_EVAL_TIME_MASK                                             0x00F0L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_RST_TIME_MASK                                              0x0F00L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT0__RT_ACK_TIME_MASK                                              0xF000L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME__SHIFT                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME__SHIFT                                          0x4
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9__SHIFT                                          0x9
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_TXDN_SETTLE_TIME_MASK                                      0x000FL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RT_PWRUP_TIME_MASK                                            0x01F0L
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_CONFIG_CNT1__RESERVED_15_9_MASK                                            0xFE00L
//DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__VALUE_MASK                                                    0x000FL
#define DPCSSYS_CR4_SUPX_DIG_RTUNE_TX_CAL_CODE__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                           0x8
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                           0x9
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_RST_MASK                                             0x0100L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_CAL_MASK                                             0x0200L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__MPLLA_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__MPLLA_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__MPLLA_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN__SHIFT                                   0x1
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                     0x3
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN__SHIFT                                0x4
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN__SHIFT                                   0x5
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN__SHIFT                                   0x6
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                        0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                           0x8
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                           0x9
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN__SHIFT                                   0xa
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN__SHIFT                                  0xb
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                      0xc
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                       0xe
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL__SHIFT                                            0xf
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_WORD_CLK_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_HDMI_CLK_EN_MASK                                     0x0002L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV_CLK_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_MASK                                       0x0008L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CLK_EN_OVRD_EN_MASK                                  0x0010L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_L_EN_MASK                                     0x0020L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_R_EN_MASK                                     0x0040L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_MASK                                          0x0080L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_RST_MASK                                             0x0100L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_CAL_MASK                                             0x0200L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV5_CLK_EN_MASK                                     0x0400L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_DIV10_CLK_EN_MASK                                    0x0800L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_MASK                                        0x1000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_MASK                                         0x4000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_0__OVRD_SEL_MASK                                              0x8000L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT__SHIFT                                       0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10__SHIFT                                      0xa
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__MPLLB_ANA_INT_MASK                                         0x03FFL
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_1__RESERVED_15_10_MASK                                        0xFC00L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP__SHIFT                                       0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT__SHIFT                                        0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14__SHIFT                                      0xe
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_PROP_MASK                                         0x007FL
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__MPLLB_CP_INT_MASK                                          0x3F80L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_OVRD_OUT_2__RESERVED_15_14_MASK                                        0xC000L
//DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                        0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                           0x4
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_COMP_RST_MASK                                          0x0001L
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_MODE_MASK                                              0x0006L
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_VALUE_MASK                                             0x3FF0L
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RTUNE_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR4_SUPX_DIG_ANA_RTUNE_OVRD_OUT__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_SUPX_DIG_ANA_STAT
#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT__SHIFT                                              0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2__SHIFT                                                   0x2
#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RT_ANA_COMP_RESULT_MASK                                                0x0001L
#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__REF_ANA_CLKDET_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR4_SUPX_DIG_ANA_STAT__RESERVED_15_2_MASK                                                     0xFFFCL
//DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN__SHIFT                                                    0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START__SHIFT                                            0x1
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START__SHIFT                                            0x2
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                            0x4
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                    0x5
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                      0x6
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                              0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                         0x8
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11__SHIFT                                           0xb
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_EN_MASK                                                      0x0001L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_FAST_START_MASK                                              0x0002L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_KICK_START_MASK                                              0x0004L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__BG_OVRD_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_MASK                                              0x0010L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN_MASK                                      0x0020L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_MASK                                        0x0040L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN_MASK                                0x0080L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_MASK                                           0x0300L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_SUPX_DIG_ANA_BG_OVRD_OUT__RESERVED_15_11_MASK                                             0xF800L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__MPLLA_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLA_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL__SHIFT                                   0x0
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN__SHIFT                                    0x6
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN__SHIFT                            0x8
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_MASK                                     0x003FL
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_MASK                                      0x0040L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_SEL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__MPLLB_PMIX_EN_OVRD_EN_MASK                              0x0100L
#define DPCSSYS_CR4_SUPX_DIG_ANA_MPLLB_PMIX_OVRD_OUT__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN__SHIFT                                          0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4__SHIFT                                         0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__EN_MASK                                                      0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RX_ACJTAG_EN_MASK                                            0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_4_MASK                                           0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL__SHIFT                                             0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN__SHIFT                                     0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN__SHIFT                                               0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_MASK                                                  0x000CL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_MASK                                                    0x00E0L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_MASK                                               0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__MPLLB_SEL_OVRD_EN_MASK                                       0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_MASK                                                 0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE__SHIFT                                               0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN__SHIFT                                             0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN__SHIFT                                          0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN__SHIFT                                          0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD__SHIFT                                   0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN__SHIFT                                0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__NYQUIST_DATA_MASK                                            0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__DISABLE_MASK                                                 0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__BEACON_EN_MASK                                               0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__EN_MASK                                                      0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_MAIN_CURSOR_MASK                                          0x03F0L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__MAIN_OVRD_EN_MASK                                            0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_EN_MASK                                            0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__ASYNC_DRV_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_MASK                                     0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__TX_VREGDRV_BYP_OVRD_EN_MASK                                  0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_1__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN__SHIFT                                           0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN__SHIFT                                           0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN__SHIFT                               0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__PRE_OVRD_EN_MASK                                             0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__TX_POST_CURSOR_MASK                                          0x1F80L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__POST_OVRD_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_EN_MASK                                             0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_2__HDMIMODE_ENABLE_OVRD_EN_MASK                                 0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT__SHIFT                                                0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN__SHIFT                                        0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN__SHIFT                                         0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN__SHIFT                                 0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN__SHIFT                                  0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN__SHIFT                          0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN__SHIFT                                       0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__CLK_RDY_OVRD_EN_MASK                                         0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_MASK                                           0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__DETECT_RX_REQ_OVRD_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__INVERT_OVRD_EN_MASK                                          0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_MASK                                                     0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__LPD_OVRD_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_MASK                                           0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_DC_COUP_EN_OVRD_EN_MASK                                   0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_MASK                                    0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__PMA_EXTENDED_FIFO_EN_OVRD_EN_MASK                            0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_MASK                                         0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MPHY_MODE_EN_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4__SHIFT                                          0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK_MASK                                                0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT_MASK                                             0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT_MASK                                          0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_4_MASK                                            0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH__SHIFT                                                 0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN__SHIFT                                         0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13__SHIFT                                        0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_MASK                                                  0x0030L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN_MASK                                          0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RATE_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_MASK                                                   0x0C00L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__WIDTH_OVRD_EN_MASK                                           0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_13_MASK                                          0xE000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ__SHIFT                                    0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN__SHIFT                                                    0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6__SHIFT                                       0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9__SHIFT                                         0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_5_0_MASK                                       0x003FL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_CDR_VCO_LOWFREQ_MASK                                      0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__EN_MASK                                                      0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RX_REF_LD_VAL_6_MASK                                         0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_1__RESERVED_15_9_MASK                                           0xFE00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN__SHIFT                                                    0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RX_VCO_LD_VAL_MASK                                           0x1FFFL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__EN_MASK                                                      0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_2__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN__SHIFT                                              0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT__SHIFT                                             0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_MASK                                              0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN_MASK                                      0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_MASK                                                0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__ALIGN_EN_OVRD_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_MASK                                               0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__CLK_SHIFT_OVRD_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_MASK                                                 0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD__SHIFT                                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN__SHIFT                                           0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN__SHIFT                                          0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN__SHIFT                                               0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC__SHIFT                                             0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN__SHIFT                                          0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10__SHIFT                                        0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_MASK                                                     0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__LPD_OVRD_EN_MASK                                             0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__INVERT_OVRD_EN_MASK                                          0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_AFE_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADAPT_DFE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__ADPT_OVRD_EN_MASK                                            0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_EN_MASK                                                 0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_ACDC_MASK                                               0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__TERM_OVRD_EN_MASK                                            0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_10_MASK                                          0xFC00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESET_OVRD_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_5__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN__SHIFT                                         0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_OVRD_EN_MASK                                           0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA__SHIFT                                        0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT__SHIFT                                   0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN_MASK                                      0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_MASK                                          0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_ASYNC_DATA_OVRD_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_MASK                                     0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RX_SQ_WEAKKEEP_OUT_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB_MASK                                       0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB_MASK                                       0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_2_MASK                                           0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ__SHIFT                                         0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE__SHIFT                                               0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET_MASK                                                   0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT_MASK                                                  0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD_MASK                                                     0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE_MASK                                                  0x00C0L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE_MASK                                                    0x0700L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH_MASK                                                   0x1800L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL_MASK                                               0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DETECT_RX_REQ_MASK                                           0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_0__DISABLE_MASK                                                 0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA__SHIFT                                         0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP__SHIFT                                        0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN_MASK                                               0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR_MASK                                          0x007EL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_EN_MASK                                             0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DATA_MASK                                           0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_ASYNC_DRV_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_VREGDRV_BYP_MASK                                          0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_1__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR_MASK                                           0x003FL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR_MASK                                          0x0FC0L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2__SHIFT                                          0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT_MASK                                             0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_2_MASK                                            0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED__SHIFT                                              0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15__SHIFT                                        0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET_MASK                                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN_MASK                                                 0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ_MASK                                                     0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD_MASK                                                     0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE_MASK                                                  0x0060L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE_MASK                                                    0x0180L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH_MASK                                                   0x0600L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_MASK                                                0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_AFE_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__ADAPT_DFE_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN_MASK                                            0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESERVED_15_15_MASK                                          0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN__SHIFT                                              0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT__SHIFT                                             0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN__SHIFT                                            0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC__SHIFT                                          0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6__SHIFT                                         0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__ALIGN_EN_MASK                                                0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__CLK_SHIFT_MASK                                               0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_EN_MASK                                              0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RX_TERM_ACDC_MASK                                            0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_6_MASK                                           0xFFC0L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN__SHIFT                                        0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL_MASK                                           0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_AFE_GAIN_MASK                                          0x0078L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_MASK                                             0x0780L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST_MASK                                        0xF800L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15__SHIFT                                     0xf
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP2_MASK                                          0x007FL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1_MASK                                          0x7F80L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__RESERVED_15_15_MASK                                       0x8000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL__SHIFT                                 0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RX_REF_LD_VAL_MASK                                   0x00FEL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RX_VCO_LD_VAL_MASK                                   0x1FFFL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4__SHIFT                                        0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK_MASK                                                    0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID_MASK                                                  0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS_MASK                                              0x000CL
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_4_MASK                                          0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON__SHIFT                                        0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON__SHIFT                                         0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN__SHIFT                             0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL__SHIFT                                           0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN__SHIFT                                   0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN__SHIFT                                             0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN__SHIFT                                     0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_MASK                                          0x0003L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_CLK_SEL_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LCC_ON_MASK                                          0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_ON_MASK                                           0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_LS_LCC_ON_OVRD_EN_MASK                               0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_MASK                                             0x00C0L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_TERM_CTL_OVRD_EN_MASK                                     0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_MASK                                               0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RX_PWM_EN_OVRD_EN_MASK                                       0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_RX_OVRD_IN_6__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE__SHIFT                                 0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN__SHIFT                         0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE__SHIFT                             0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN__SHIFT                     0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE__SHIFT                                     0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN__SHIFT                             0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE__SHIFT                                  0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN__SHIFT                          0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER__SHIFT                                           0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN__SHIFT                                0xb
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD__SHIFT                                0xc
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                             0xd
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14__SHIFT                                        0xe
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_MASK                                     0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RPTR_EN_MASTER_LANE_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_MASK                                   0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_EN_OTHER_LANE_OVRD_EN_MASK                           0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_MASK                               0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__DIG_CLK_STATE_MASTER_LANE_OVRD_EN_MASK                       0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_MASK                                       0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_MASTER_LANE_ORVD_EN_MASK                               0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_MASK                                    0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__SHIFT_ACK_OTHER_LANE_OVRD_EN_MASK                            0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_MASK                                             0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__LANE_MASTER_OVRD_IN_EN_MASK                                  0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_MASK                                  0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                               0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_IN_5__RESERVED_15_14_MASK                                          0xC000L
//DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT__SHIFT                                    0x4
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT__SHIFT                                            0x6
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT__SHIFT                                        0x8
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10__SHIFT                                       0xa
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_MASK                                            0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RPTR_EN_OUT_OVRD_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_EN_OUT_OVRD_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_MASK                                      0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__DIG_CLK_STATE_OUT_OVRD_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_MASK                                              0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_OUT_OVRD_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_MASK                                          0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__SHIFT_ACK_OUT_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_TX_OVRD_OUT_1__RESERVED_15_10_MASK                                         0xFC00L
//DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA
#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RX_DWORD_OCLA_DATA_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ASIC_OCLA__RESERVED_15_2_MASK                                                   0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x5
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x7
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN__SHIFT                      0x9
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10__SHIFT                                  0xa
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN_MASK                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD_MASK                               0x0002L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN_MASK                                 0x0004L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET_MASK                                  0x0010L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN_MASK                              0x0020L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN_MASK                                    0x0080L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET_MASK                                0x0100L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_COMP_CAL_EN_MASK                        0x0200L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_10_MASK                                    0xFC00L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN__SHIFT                        0x9
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10__SHIFT                                   0xa
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_COMP_CAL_EN_MASK                          0x0200L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_10_MASK                                     0xFC00L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0x3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x5
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x7
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x9
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN__SHIFT                        0xa
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN_MASK                                0x0001L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD_MASK                                 0x0002L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN_MASK                              0x0008L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET_MASK                                    0x0010L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN_MASK                                0x0020L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN_MASK                                      0x0080L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET_MASK                                  0x0100L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST_MASK                                 0x0200L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_COMP_CAL_EN_MASK                          0x0400L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN__SHIFT                                     0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME_MASK                               0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_MASK                                       0xFF00L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0__SHIFT                         0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME_14_0_MASK                           0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT_MASK                           0x8000L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL__SHIFT                                       0xd
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME_12_0_MASK                         0x1FFFL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__DTB_SEL_MASK                                         0xE000L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15__SHIFT                        0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13__SHIFT                         0x3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VCM_HOLD_TIME_17_15_MASK                          0x0007L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VBOOST_DIS_TIME_13_MASK                           0x0008L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE__SHIFT                     0xf
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME_MASK                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__SKIP_TX_VCM_HOLD_GS_PULSE_MASK                       0x8000L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET__SHIFT                                 0xa
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME__SHIFT                                 0xb
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME__SHIFT                             0xd
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RXDET_TIME_MASK                                   0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__FAST_TX_RXDET_MASK                                   0x0400L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_RESET_TIME_MASK                                   0x1800L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_SERIAL_EN_TIME_MASK                               0x6000L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_ADDR__ADDR_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_CR_BANK_DATA__DATA_MASK                                           0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__CTRL_MASK                                               0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_CTRL__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__CTRL_MASK                                              0x0003L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_RANGE__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ__SHIFT                                               0x3
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD__SHIFT                                          0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD__SHIFT                                         0x5
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT__SHIFT                                           0x6
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__SEL_MASK                                                 0x0007L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__REQ_MASK                                                 0x0008L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__CTRL_UPD_MASK                                            0x0010L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RANGE_UPD_MASK                                           0x0020L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__BIN_HOT_MASK                                             0x0040L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_SEL__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ACK__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_PWRCTL_DCC_DAC_ADDR__ADDR_MASK                                               0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE__SHIFT                        0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS__SHIFT                                    0x8
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_16B_MODE_MASK                          0x000FL
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_20B_MODE_MASK                          0x00F0L
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_FIFO_BYPASS_MASK                                      0x0100L
#define DPCSSYS_CR4_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR_MASK                                                  0x0010L
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__PAT0_MASK                                                         0x7FE0L
#define DPCSSYS_CR4_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15_MASK                                               0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0__SHIFT                                       0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_1_MASK                                         0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_0_MASK                                         0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2__SHIFT                                      0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11__SHIFT                                  0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN_MASK                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN_MASK                            0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_2_MASK                                        0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN_MASK                                 0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_4_MASK                                        0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN_MASK                               0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST_MASK                               0x0080L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST_MASK                                0x0100L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN_MASK                             0x0200L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_11_MASK                                    0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4__SHIFT                                       0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11__SHIFT                                   0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN_MASK                              0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_2_MASK                                         0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN_MASK                                   0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_4_MASK                                         0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN_MASK                                 0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN_MASK                                   0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST_MASK                                 0x0080L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST_MASK                                  0x0100L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN_MASK                               0x0200L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN_MASK                                   0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_11_MASK                                     0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME__SHIFT                               0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_AFE_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_AFE_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_VREG_EN_TIME_MASK                                 0x1F80L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_VREG_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME__SHIFT                                0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME__SHIFT                            0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11__SHIFT                                0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_CLK_EN_TIME_MASK                                  0x003FL
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__FAST_RX_CLK_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RX_FAST_START_TIME_MASK                              0x0780L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2__RESERVED_15_11_MASK                                  0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2__SHIFT                                    0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME__SHIFT                              0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME__SHIFT                             0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_RATE_TIME_MASK                                    0x0003L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RSVD_3_7_2_MASK                                      0x00FCL
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_CDR_EN_TIME_MASK                                  0x0F00L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_EN_TIME_MASK                                0x3000L
#define DPCSSYS_CR4_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_3__RX_DESER_DIS_TIME_MASK                               0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15__SHIFT                              0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_MASK                        0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT_MASK                        0x01C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT_MASK                       0x0E00L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD_MASK                              0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD_MASK                         0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE_MASK                        0x4000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__RESERVED_15_15_MASK                                0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL_MASK                               0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST_MASK                               0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST_MASK                                0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN_MASK                             0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE_MASK                          0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG_MASK                                   0x01E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL_MASK                                       0xFE00L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL__SHIFT                         0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS__SHIFT                         0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_START_VAL_MASK                           0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREQ_TUNE_CAL_STEPS_MASK                           0x3C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL_MASK                     0x4000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL_MASK                               0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME__SHIFT                         0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_STARTUP_TIME_MASK                           0x007FL
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME_MASK                            0x0780L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME_MASK                        0x7800L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT_MASK                              0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3__SHIFT                               0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME_MASK                       0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_3_MASK                                 0xFFF8L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14__SHIFT                                  0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE_MASK                              0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD_MASK                                0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN_MASK                                0x0800L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP_MASK                                0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_14_MASK                                    0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE_MASK                                  0x000FL
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST_MASK                                   0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST_MASK                                    0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE_MASK                                   0x0080L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST_MASK                                     0x0100L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9_MASK                                     0xFE00L
//DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL_MASK                                    0x1FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST_MASK                                   0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT_MASK                                    0x4000L
#define DPCSSYS_CR4_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK
#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK__SHIFT                               0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10__SHIFT                               0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__XAUI_COMM_MASK_MASK                                 0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK__RESERVED_15_10_MASK                                 0xFC00L
//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5__SHIFT                                              0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__MODE_MASK                                                         0x000FL
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__SYNC_MASK                                                         0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_5_MASK                                                0xFFE0L
//DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__COUNT_MASK                                                        0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_LBERT_ERR__OV14_MASK                                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11__SHIFT                                         0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_MASK                                                 0x0003L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE_MASK                                               0x000CL
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL_MASK                                                0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE_MASK                                         0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__ALWAYS_REALIGN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL_MASK                                                  0x0780L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_11_MASK                                           0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0_MASK                                             0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1_MASK                                             0xFC00L
//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0_MASK                                              0x01FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1_MASK                                              0xFE00L
//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0_MASK                                            0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1_MASK                                            0x0038L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0_MASK                                            0x01C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN_MASK                                           0x0200L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE_MASK                                          0x1C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE_MASK                                          0xE000L
//DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1_MASK                                            0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0_MASK                                             0x0038L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1_MASK                                             0x01C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0_MASK                                             0x0E00L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1_MASK                                             0x7000L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15_MASK                                           0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE_MASK                                                    0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE_MASK                                                    0x0038L
#define DPCSSYS_CR4_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6_MASK                                                 0xFFC0L
//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__VAL_MASK                                                          0x3FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN_MASK                                        0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND_MASK                                     0x07FEL
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND_MASK                                     0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10_MASK                                       0xFC00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN__SHIFT                                  0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1_MASK                                          0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1_MASK                                          0x3C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1_MASK                                          0x4000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__ADPT_CLK_DIV4_EN_MASK                                    0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE__SHIFT                               0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12__SHIFT                                    0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1_MASK                                         0x007FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__FAST_AFE_DFE_SETTLE_MASK                                 0x0080L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL_MASK                                  0x0700L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN_MASK                                   0x0800L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_12_MASK                                      0xF000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0_MASK                                         0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10_MASK                                      0xFC00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN_MASK                                             0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN_MASK                                              0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN_MASK                                              0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN_MASK                                              0x0F80L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN_MASK                                            0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN_MASK                                              0x4000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL_MASK                                       0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH_MASK                                             0x000FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH_MASK                                              0x00F0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH_MASK                                             0x0F00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH_MASK                                             0xF000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH_MASK                                             0x000FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH_MASK                                             0x00F0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH_MASK                                             0x0F00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET_MASK                                           0xF000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU_MASK                                             0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU_MASK                                              0x0038L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU_MASK                                              0x01C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_MASK                                         0x0E00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY_MASK                                  0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH_MASK                                          0xE000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT_MASK                                         0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH_MASK                                        0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW_MASK                                         0x7C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU_MASK                                             0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU_MASK                                             0x0038L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU_MASK                                             0x01C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU_MASK                                             0x0E00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU_MASK                                             0x7000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15_MASK                                      0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT_MASK                                   0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT_MASK                                   0xFF00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5__SHIFT                                   0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT_MASK                                      0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA_MASK                                      0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST_MASK                               0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE_MASK                                0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1_MASK                                     0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_5_MASK                                     0xFFE0L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON__SHIFT                                          0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9__SHIFT                                     0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE_MASK                                       0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DON_MASK                                            0x0100L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_9_MASK                                       0xFE00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE_MASK                                       0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE_MASK                                           0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14__SHIFT                                   0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE_MASK                               0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE_MASK                                0x1C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE_MASK                                          0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_14_MASK                                     0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE_MASK                             0x1FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE_MASK                                      0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14_MASK                                 0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE_MASK                             0x0FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE_MASK                                      0x1000L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__DFE_DATA_EVEN_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST__SHIFT                0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__DFE_DATA_ODD_VDAC_OFST_MASK                  0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST__RESERVED_15_8_MASK                           0xFF00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E_MASK                       0x000FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O_MASK                        0x000FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4_MASK                               0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST_MASK              0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8_MASK                         0xFF00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST_MASK                0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8_MASK                          0xFF00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL__SHIFT                                 0x8
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLO_LVL_MASK                                   0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL__E_SLE_LVL_MASK                                   0xFF00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1_MASK                                          0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC__SHIFT                                   0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC__SHIFT                                0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15__SHIFT                                0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T1_IDAC_MASK                                     0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DFE_T2_IDAC_MASK                                     0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__DCC_START_IDAC_MASK                                  0x7C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_1__RESERVED_15_15_MASK                                  0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__DFE_DAT_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_2__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC__SHIFT                             0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC__SHIFT                              0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10__SHIFT                                0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_EVEN_VDAC_MASK                               0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__DFE_ERR_ODD_VDAC_MASK                                0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_DAC_CTRL_SEL_3__RESERVED_15_10_MASK                                  0xFC00L
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_ADDR__ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_ADPTCTL_CR_BANK_DATA__DATA_MASK                                              0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START_MASK                                                0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0_MASK                                            0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0_MASK                                     0x001FL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0_MASK                                         0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16_MASK                                         0x3C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY_MASK                                              0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN_MASK                                          0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0_MASK                                     0x003EL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0_MASK                                         0x07C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN_MASK                                     0x0800L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA__SHIFT                                     0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0_MASK                                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_VGA_MASK                                       0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL_MASK                                           0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL_MASK                                            0x0018L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN_MASK                                            0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL_MASK                                           0x03C0L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL_MASK                                            0x1C00L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL_MASK                                          0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE_MASK                                           0x4000L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN_MASK                                                 0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7__SHIFT                                          0x7
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN_MASK                                           0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN_MASK                                           0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN_MASK                                           0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN_MASK                                           0x0010L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN_MASK                                           0x0020L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN_MASK                                           0x0040L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__RESERVED_8_7_MASK                                            0x0180L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE_MASK                                                0x0200L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN_MASK                                             0x0400L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL_MASK                                            0x1800L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR_MASK                                            0x2000L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL_MASK                                                 0xC000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_MASK                                               0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE_MASK                                          0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6_MASK                                             0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6__SHIFT                                  0x6
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT_MASK                                     0x0007L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT_MASK                                      0x0038L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_6_MASK                                    0xFFC0L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5_MASK                                        0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5_MASK                                    0x7FFFL
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15_MASK                                         0x8000L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3__SHIFT                                         0x3
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2_MASK                                          0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2_MASK                                             0x0002L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT_MASK                                    0x0004L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_3_MASK                                           0xFFF8L
//DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP_MASK                                                0x0001L
#define DPCSSYS_CR4_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1_MASK                                           0xFFFEL
//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL__SHIFT                                              0x0
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL__SHIFT                                         0x1
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2__SHIFT                                           0x2
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_POL_MASK                                                0x0001L
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RX_PWM_DATA_POL_MASK                                           0x0002L
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_PWM_CTL__RESERVED_15_2_MASK                                             0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RX_TERM_LCC_CNT_MASK                                       0x0007L
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_TERM_LS_CTL__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4__SHIFT                            0x4
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__PWM_CLK_STABLE_CNT_MASK                         0x000FL
#define DPCSSYS_CR4_LANEX_DIG_MPHY_RX_ANA_PWM_CLK_STABLE_CNT__RESERVED_15_4_MASK                              0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN__SHIFT                                          0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN__SHIFT                                        0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD__SHIFT                                         0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN__SHIFT                                      0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN__SHIFT                                     0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN__SHIFT                                     0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET__SHIFT                                            0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE__SHIFT                                        0xa
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED__SHIFT                                                0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN__SHIFT                                              0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN__SHIFT                                             0xe
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN__SHIFT                                              0xf
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_SHIFT_MASK                                          0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_EN_MASK                                            0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_REFGEN_EN_MASK                                          0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_VCM_HOLD_MASK                                           0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_CLK_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_WORD_CLK_EN_MASK                                        0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLA_CLK_EN_MASK                                       0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_MPLLB_CLK_EN_MASK                                       0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_RESET_MASK                                              0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_SERIAL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_ANA_DATA_RATE_MASK                                          0x0C00L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__RESERVED_MASK                                                  0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_DIV4_EN_MASK                                                0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_RXDET_EN_MASK                                               0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT__TX_OVRD_EN_MASK                                                0x8000L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN__SHIFT                               0xa
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC__SHIFT                                    0xb
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14__SHIFT                                0xe
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_CODE_MASK                                    0x03FFL
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_TERM_OVRD_EN_MASK                                 0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_MASK                                      0x1800L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__TX_DRV_SRC_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_OVRD_OUT__RESERVED_15_14_MASK                                  0xC000L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK__SHIFT                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_DN_CLK_MASK                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__TX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                    0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0__SHIFT                       0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN__SHIFT                                      0xf
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_LOAD_CLK_MASK                                      0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_ANA_CTRL_LEG_PULL_EN_13_0_MASK                         0x7FFEL
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0__TX_EQ_OVRD_EN_MASK                                        0x8000L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14__SHIFT                      0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6__SHIFT                                      0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__TX_ANA_CTRL_LEG_PULL_EN_19_14_MASK                        0x003FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1__RESERVED_15_6_MASK                                        0xFFC0L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL__SHIFT                             0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE__SHIFT                                    0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13__SHIFT                                     0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_MASK                                             0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_EQ_MUX_SEL_MASK                               0x0078L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__TX_ANA_CTRL_PRE_MASK                                      0x1F80L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2__RESERVED_15_13_MASK                                       0xE000L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9__SHIFT                                      0x9
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__TX_ANA_CTRL_POST_MASK                                     0x01FFL
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3__RESERVED_15_9_MASK                                        0xFE00L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4__SHIFT                      0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4__TX_ANA_CTRL_LEG_PULL_DIR_19_4_MASK                        0xFFFFL
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0__SHIFT                       0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4__SHIFT                                      0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__TX_ANA_CTRL_LEG_PULL_DIR_3_0_MASK                         0x000FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_5__RESERVED_15_4_MASK                                        0xFFF0L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                    0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                      0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN__SHIFT                                0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN__SHIFT                                       0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN__SHIFT                                      0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9__SHIFT                                       0x9
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_MASK                                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_MASK                                      0x0006L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_WORD_CLK_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_MASK                                        0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_ANA_ADAPTATION_EN_MASK                                  0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_LBK_CLK_EN_MASK                                         0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RX_CTL_OVRD_EN_MASK                                        0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CTL_OVRD_OUT__RESERVED_15_9_MASK                                         0xFE00L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN__SHIFT                                  0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN__SHIFT                                       0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN__SHIFT                                       0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN__SHIFT                                      0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START__SHIFT                                   0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8__SHIFT                                       0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_AFE_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_VREG_EN_MASK                                    0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_DCC_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CLK_EN_MASK                                         0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_CDR_EN_MASK                                         0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_DESERIAL_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_PWR_OVRD_EN_MASK                                        0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RX_ANA_FAST_START_MASK                                     0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_PWR_OVRD_OUT__RESERVED_15_8_MASK                                         0xFF00L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                                0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN__SHIFT                                0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                              0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                                0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                               0xe
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_MASK                                   0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_MASK                                  0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_VCO_CDR_OVRD_EN_MASK                                  0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_FREQ_TUNE_MASK                                0x1FF8L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_MASK                                  0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_MASK                                 0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0__RX_CDR_FREQ_TUNE_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ__SHIFT                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_LOWFREQ_MASK                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RX_ANA_VCO_CNTR_PD_MASK                                  0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                          0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE__SHIFT              0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK_MASK                            0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__CDR_FREQ_TUNE_CLK_SELF_CLEAR_DISABLE_MASK                0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL__SHIFT                                          0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN__SHIFT                                         0xa
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED__SHIFT                                                     0xb
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN__SHIFT                                         0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE__SHIFT                                              0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN__SHIFT                                           0xf
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXA_SEL_MASK                                            0x001FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MUXB_SEL_MASK                                            0x03E0L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_LPFBYP_EN_MASK                                           0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RESERVED_MASK                                                       0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_SLICER_CAL_EN_MASK                                           0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_MODE_MASK                                                0x6000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_CAL__RX_ANA_CAL_COMP_EN_MASK                                             0x8000L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL_MASK                                       0x00FFL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                               0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD_MASK                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                             0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5__SHIFT                                       0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL_MASK                               0x001FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_DAC_CTRL_SEL__RESERVED_15_5_MASK                                         0xFFE0L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL__SHIFT                                   0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED__SHIFT                                             0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN__SHIFT                                       0xb
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12__SHIFT                                       0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_ATT_LVL_MASK                                     0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_ANA_AFE_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_MASK                                               0x0780L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RX_AFE_OVRD_EN_MASK                                         0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_ATT_VGA__RESERVED_15_12_MASK                                         0xF000L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED__SHIFT                                                0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST__SHIFT                                   0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8__SHIFT                                           0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_MASK                                                  0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RX_ANA_AFE_CTLE_BOOST_MASK                                     0x00F8L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_AFE_CTLE__RESERVED_15_8_MASK                                             0xFF00L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                           0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK__SHIFT                                        0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE__SHIFT                                         0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN__SHIFT                                        0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE__SHIFT                                0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14__SHIFT                                             0xe
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_EN_MASK                                              0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_SEL_MASK                                             0x0006L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PH_CLK_MASK                                          0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_PHASE_MASK                                           0x0FF0L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_ANA_SCOPE_CLK_EN_MASK                                          0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RX_SCOPE_SELF_CLEAR_DISABLE_MASK                                  0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SCOPE__RESERVED_15_14_MASK                                               0xC000L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                                 0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                                 0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                        0x9
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E_MASK                                   0x000FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O_MASK                                   0x00F0L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_SLICER_CTRL__RESERVED_15_9_MASK                                          0xFE00L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST__SHIFT                       0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7__SHIFT                                0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RX_ANA_IQ_PHASE_ADJUST_MASK                         0x007FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST__RESERVED_15_7_MASK                                  0xFF80L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN__SHIFT                               0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RX_ANA_IQ_SENSE_EN_MASK                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                       0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT                  0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN_MASK                         0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE_MASK                    0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN__SHIFT                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE__SHIFT         0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2__SHIFT                         0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RX_ANA_AFE_UPDATE_EN_MASK                    0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__AFE_UPDATE_SELF_CLEAR_DISABLE_MASK           0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE__RESERVED_15_2_MASK                           0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK__SHIFT                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE__SHIFT             0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2__SHIFT                               0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RX_ANA_IQ_PHASE_ADJUST_CLK_MASK                    0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__PHASE_ADJUST_SELF_CLEAR_DISABLE_MASK               0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK__RESERVED_15_2_MASK                                 0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                       0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT__SHIFT                                       0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN__SHIFT                                         0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT__SHIFT                                          0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA__SHIFT                                          0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT__SHIFT                                      0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX__SHIFT                                         0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_SHIFT_ACK_MASK                                         0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETP_RESULT_MASK                                         0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_RXDETM_RESULT_MASK                                         0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_LOOPBACK_EN_MASK                                           0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CLK_LB_EN_MASK                                             0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_CAL_RESULT_MASK                                            0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__RX_ANA_SCOPE_DATA_MASK                                            0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_DCC_CAL_RESULT_MASK                                        0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_0__TX_ANA_CTRL_EQ_MUX_MASK                                           0xFF00L
//DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13__SHIFT                                             0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RX_ANA_VCO_CNTR_MASK                                              0x1FFFL
#define DPCSSYS_CR4_LANEX_DIG_ANA_STATUS_1__RESERVED_15_13_MASK                                               0xE000L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                               0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                                 0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE_MASK                                    0x003FL
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN_MASK                                 0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7_MASK                                   0xFF80L
//DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                               0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT            0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                             0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_MASK                                 0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE_MASK              0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2_MASK                               0xFFFCL
//DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH__SHIFT                                  0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP__SHIFT                                   0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN__SHIFT                           0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN__SHIFT                                         0x7
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL__SHIFT                                    0x9
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN__SHIFT                            0xb
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12__SHIFT                                        0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_MASK                                    0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_TRESH_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_MASK                                     0x0030L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_SQ_CTRL_RESP_OVRD_EN_MASK                             0x0040L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_MASK                                           0x0080L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_EN_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_MASK                                      0x0600L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RX_ANA_PWM_CLK_SEL_OVRD_EN_MASK                              0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ANA_MPHY_OVRD_OUT__RESERVED_15_12_MASK                                          0xF000L
//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                         0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xa
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN__SHIFT                              0xb
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                      0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_HF_CAL_TUNE_MASK                           0x03F0L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x0400L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_MASK                                0x0800L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RX_ANA_SIGDET_CAL_EN_OVRD_EN_MASK                        0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_1__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH__SHIFT                           0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN__SHIFT                        0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN__SHIFT                0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE__SHIFT                            0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN__SHIFT                    0xc
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_MASK                             0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_THRESH_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_MASK                          0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_LF_FILTER_EN_OVRD_EN_MASK                  0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_MASK                              0x0FC0L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RX_ANA_SIGDET_CAL_TUNE_OVRD_EN_MASK                      0x1000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_SIGDET_OVRD_OUT_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE__SHIFT                            0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN__SHIFT                    0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN__SHIFT                          0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN__SHIFT                  0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL__SHIFT                             0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN__SHIFT                     0xd
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN__SHIFT                          0xe
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN__SHIFT                  0xf
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_MASK                              0x0003L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_RANGE_OVRD_EN_MASK                      0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_MASK                            0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_COMP_EN_OVRD_EN_MASK                    0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_MASK                               0x1FE0L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_OVRD_EN_MASK                       0x2000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_MASK                            0x4000L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT__TX_ANA_DCC_CAL_CTRL_EN_OVRD_EN_MASK                    0x8000L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL__SHIFT                       0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN__SHIFT               0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP__SHIFT                           0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN__SHIFT                   0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6__SHIFT                                 0x6
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_MASK                         0x0007L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CAL_CTRL_SEL_OVRD_EN_MASK                 0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_MASK                             0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__TX_ANA_DCC_CLK_COMP_OVRD_EN_MASK                     0x0020L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_DCC_DAC_OVRD_OUT_2__RESERVED_15_6_MASK                                   0xFFC0L
//DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START__SHIFT                                     0x0
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN__SHIFT                             0x1
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN__SHIFT                                          0x2
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN__SHIFT                                          0x4
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5__SHIFT                                         0x5
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_MASK                                       0x0001L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ANA_FAST_START_OVRD_EN_MASK                               0x0002L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_MASK                                            0x0004L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_CLK_LB_EN_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__TX_ACJTAG_EN_MASK                                            0x0010L
#define DPCSSYS_CR4_LANEX_DIG_ANA_TX_OVRD_OUT_2__RESERVED_15_5_MASK                                           0xFFE0L
//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__OVRD_CLK_SHIFT__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__CLK_SHIFT_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_MUX__SHIFT                                           0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__MEAS_ATB_CAL_COMP__SHIFT                                          0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__OVRD_VCM_HOLD__SHIFT                                              0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__VCM_HOLD_REG__SHIFT                                               0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__PULL_UP_REG__SHIFT                                                0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__PULL_DN_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_MEAS__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__OVRD_TX_LOOPBACK__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__LOOPBACK_EN_REG__SHIFT                                             0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__REFGEN_EN_REG__SHIFT                                               0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__CLK_DIV_EN_REG__SHIFT                                              0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__DATA_EN_REG_INT__SHIFT                                             0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__CLK_EN_REG__SHIFT                                                  0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__SERIAL_EN_REG__SHIFT                                               0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__OVRD_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_PWR_OVRD__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__DRV_SOURCE_REG__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__OVRD_ALT_BUS__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__ATB_S_ENABLE__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__TX_ALT_RINGO__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__JTAG_DATA_REG__SHIFT                                                0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_ALT_BUS__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_ATB1
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__MEAS_ATB_GD__SHIFT                                                     0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__MEAS_ATB_VDDH__SHIFT                                                   0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__OVERRIDE_RXDETREF__SHIFT                                               0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__MEAS_ATB_VPTX__SHIFT                                                   0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__OVERRIDE_REGREF__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG_DRV__SHIFT                                               0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__MEAS_ATB_VREG__SHIFT                                                   0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__MEAS_ATB_VPH_HALF__SHIFT                                               0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_ATB2
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__MEAS_ATB_VCM__SHIFT                                                    0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_CM__SHIFT                                            0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__MEAS_ATB_CAL_VDAC_DIFF__SHIFT                                          0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__MEAS_ATB_TXM__SHIFT                                                    0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__MEAS_ATB_TXP__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__MEAS_ATB_RXDETREF__SHIFT                                               0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__LFPS_HIGH_PRIORITY__SHIFT                                              0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__OSC_DIV4_EN__SHIFT                                                     0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_ATB2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__DCC_DAC_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_DAC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0__SHIFT                                                        0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_SEL__SHIFT                                      0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_SEL_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_CTRL_EN__SHIFT                                       0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__DCC_DAC_CTRL_EN_REG__SHIFT                                        0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__OVRD_DCC_DAC_REG__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__NC0_MASK                                                          0x0001L
#define DPCSSYS_CR4_LANEX_ANA_TX_DCC_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__TERM_CODE_REG_70__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__VREG_BOOST_1__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_UPDATE_TERM__SHIFT                                      0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__UPDATE_TERM_REG__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_RESET_TERM__SHIFT                                       0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESET_TERM_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__OVRD_TERM_CODE__SHIFT                                        0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__TERM_CODE_REG_98__SHIFT                                      0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8__SHIFT                                         0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_TERM_CODE_CTRL__RESERVED_15_8_MASK                                           0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__VREG_BOOST_0__SHIFT                                                0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__CLK_LB_EN_REG__SHIFT                                               0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__OVRD_LB_EN__SHIFT                                                  0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__MPLLB_CLK_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__MPLLA_CLK_EN_REG__SHIFT                                            0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__OVRD_MPLLAB_EN__SHIFT                                              0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__WORD_CLK_EN_REG__SHIFT                                             0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__OVRD_WORD_CLK_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_OVRD_CLK__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_MISC1
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__MEAS_ATB_CAL_CLK_ALIGN__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__OVRD_DCC_DAC_CTRL_RANGE__SHIFT                                        0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__DCC_DAC_CTRL_RANGE_REG__SHIFT                                         0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__OVRD_VREF_SEL__SHIFT                                                  0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__VREF_SEL_REG__SHIFT                                                   0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__FORCE_ATB_TXM__SHIFT                                                  0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__FORCE_ATB_TXP__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_MISC2
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__TX_PEAKING_LVL__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__VREG_CP_GAIN_CTRL__SHIFT                                              0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__TX_SLEW_EN__SHIFT                                                     0x3
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__EN_INV_POST__SHIFT                                                    0x4
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__EN_INV_PRE__SHIFT                                                     0x5
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__TX_VREG_EN_BYP__SHIFT                                                 0x6
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__TX_VDRIVER_PULLDN_EN__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_MISC3
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__TX_VREG_OVRD_RING_CTRL__SHIFT                                         0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__TX_DCC_LOWV__SHIFT                                                    0x1
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2__SHIFT                                                          0x2
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__NC7_2_MASK                                                            0x00FCL
#define DPCSSYS_CR4_LANEX_ANA_TX_MISC3__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANEX_ANA_TX_RESERVED4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_CLK_1
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__CDR_VCO_STARTUP_CODE__SHIFT                                           0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__CDR_VCO_TEMP_COMP_EN__SHIFT                                           0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__CDR_VCO_USE_UNCAL_BIAS__SHIFT                                         0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__OVERRIDE_CDR_EN__SHIFT                                                0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__OVRD_CLK_EN__SHIFT                                                    0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__CLK_EN_REG__SHIFT                                                     0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7__SHIFT                                                            0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__NC7_MASK                                                              0x0080L
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_1__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_CLK_2
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__IQ_PHASE_ADJUST_REG__SHIFT                                            0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__OVRD_IQ_PHASE_ADJUST__SHIFT                                           0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RX_LOOPBACK_CLK_REG__SHIFT                                            0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__OVRD_RX_LOOPBACK_CLK__SHIFT                                           0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8__SHIFT                                                  0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_CLK_2__RESERVED_15_8_MASK                                                    0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__OVRD_WORD_CLK_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__WORD_CLK_EN_REG__SHIFT                                              0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__PHDET_ODD_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__PHDET_EVEN_REG__SHIFT                                               0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__SIGDET_VREF_EXT_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5__SHIFT                                                        0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__NC7_5_MASK                                                          0x00E0L
#define DPCSSYS_CR4_LANEX_ANA_RX_CDR_DES__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL
#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_O_REG__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RX_SLICER_CTRL_E_REG__SHIFT                                        0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8__SHIFT                                               0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_SLC_CTRL__RESERVED_15_8_MASK                                                 0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__OVRD_ACJT_EN__SHIFT                                               0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ACJT_EN_REG__SHIFT                                                0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__OVRD_AFE_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__AFE_EN_REG__SHIFT                                                 0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__AFE_CM_SEL__SHIFT                                                 0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__ATT_PULLDN_EN__SHIFT                                              0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7__SHIFT                                                      0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__NC7_7_MASK                                                        0x0080L
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__OVRD_DFE_EN__SHIFT                                                0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__DFE_EN_REG__SHIFT                                                 0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__OVRD_DESERIAL_EN__SHIFT                                           0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__DESERIAL_EN_REG__SHIFT                                            0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__OVRD_LOOPBACK_EN__SHIFT                                           0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__LOOPBACK_EN_REG__SHIFT                                            0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__OVRD_FAST_START__SHIFT                                            0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__FAST_START_REG__SHIFT                                             0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_PWR_CTRL2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_SQ
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__SQ_CTRL_RESP_REG__SHIFT                                                  0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_RESP__SHIFT                                                 0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3__SHIFT                                                             0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__SQ_CTRL_TRESH_REG__SHIFT                                                 0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__OVRD_SQ_CTRL_TRESH__SHIFT                                                0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__AFE_LOOPBACK_SEL__SHIFT                                                  0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8__SHIFT                                                     0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__NC4_3_MASK                                                               0x0018L
#define DPCSSYS_CR4_LANEX_ANA_RX_SQ__RESERVED_15_8_MASK                                                       0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_CAL1
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__DFE_TAPS_EN_REG__SHIFT                                                 0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__OVRD_DFE_TAPS_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__CAL_MUXB_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__OVRD_CAL_MUXB_SEL__SHIFT                                               0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL1__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_CAL2
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__AFE_PD_EQ_OFFSET__SHIFT                                                0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__CAL_IDACS_USE_UNCAL__SHIFT                                             0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__CAL_MUXA_SEL_REG__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__OVRD_CAL_MUXA_SEL__SHIFT                                               0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8__SHIFT                                                   0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_CAL2__RESERVED_15_8_MASK                                                     0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_VCO__SHIFT                                       0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_CLK__SHIFT                                       0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__OVERRIDE_REGREF_IQC__SHIFT                                       0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__BOOST_REGREF_IQC__SHIFT                                          0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_SLICER_CTRL__SHIFT                                       0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__OVRD_RX_TERM_AC_DCZ__SHIFT                                       0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RX_TERM_AC_DCZ_REG__SHIFT                                        0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8__SHIFT                                             0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_REGREF__RESERVED_15_8_MASK                                               0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__MASTER_ATB_EN__SHIFT                                              0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VP__SHIFT                                                0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_GD__SHIFT                                                0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_VCO__SHIFT                                          0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_CLK__SHIFT                                          0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__MEAS_ATB_VREG_IQC__SHIFT                                          0x5
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__REGS_FB_DIV_CTRL__SHIFT                                           0x6
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RX_VREG_CLK_BYPASS__SHIFT                                         0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__MEAS_ATB_RX__SHIFT                                                0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS2__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_GD__SHIFT                                        0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VIREF_200U__SHIFT                                0x1
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_VIBIAS_CDR_VCO__SHIFT                                    0x2
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CDR_VCO_VOSC__SHIFT                                      0x3
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__MEAS_ATB_CAL_MUX__SHIFT                                           0x4
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RX_VREG_OVERRIDE_RING_CTRL__SHIFT                                 0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS3__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__MEAS_ATB_CAL_VREF__SHIFT                                          0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7__SHIFT                                                        0x7
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__NC7_MASK                                                          0x0080L
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_MEAS4__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__FRC_ATB_CAL_VREF__SHIFT                                             0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8__SHIFT                                                0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_ATB_FRC__RESERVED_15_8_MASK                                                  0xFF00L
//DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1
#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0__SHIFT                                                      0x0
#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8__SHIFT                                              0x8
#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__NC7_0_MASK                                                        0x00FFL
#define DPCSSYS_CR4_LANEX_ANA_RX_RESERVED1__RESERVED_15_8_MASK                                                0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN__SHIFT                                            0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN__SHIFT                                            0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                                   0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                                   0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                                  0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                                0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                                 0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__PSTATE_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__LPD_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__WIDTH_MASK                                                0x0018L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__RATE_MASK                                                 0x00E0L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLLB_SEL_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MPLL_EN_MASK                                              0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__OVRD_EN_MASK                                              0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                     0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                     0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                    0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                                  0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                                   0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                             0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                              0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                                0x0F00L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                               0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                                0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_1__RESERVED_15_15_MASK                                     0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD__SHIFT                                                 0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE__SHIFT                                                0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL__SHIFT                                           0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN__SHIFT                                             0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE__SHIFT                                    0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ__SHIFT                                           0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESET_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__REQ_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__PSTATE_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__LPD_MASK                                                   0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__WIDTH_MASK                                                 0x0060L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RATE_MASK                                                  0x0380L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLLB_SEL_MASK                                             0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MPLL_EN_MASK                                               0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLA_STATE_MASK                                      0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__MSTR_MPLLB_STATE_MASK                                      0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__DETRX_REQ_MASK                                             0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5__SHIFT                                     0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__DETRX_RESULT_MASK                                        0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__EN_CTL_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_OUT__RESERVED_15_5_MASK                                       0xFFE0L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE__SHIFT                                             0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD__SHIFT                                                0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN__SHIFT                                            0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN__SHIFT                                       0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN__SHIFT                                       0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                      0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                       0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R__SHIFT                              0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14__SHIFT                                     0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RATE_MASK                                                 0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__WIDTH_MASK                                                0x000CL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__PSTATE_MASK                                               0x0030L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LPD_MASK                                                  0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__OVRD_EN_MASK                                              0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_AFE_EN_MASK                                         0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__ADAPT_DFE_EN_MASK                                         0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                        0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                         0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_VAL_R_MASK                                0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RX_DATA_EN_OVRD_EN_R_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN__RESERVED_15_14_MASK                                       0xC000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                       0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                     0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                                   0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESET_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_VAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__REQ_OVRD_EN_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                            0x0070L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_MASK                                          0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                                  0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__ADAPT_CONT_MASK                                         0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                        0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                       0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_1__RESERVED_15_13_MASK                                     0xE000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                             0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                    0x1FFFL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                                 0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                               0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                               0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                    0x007FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                                 0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_IN_3__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE__SHIFT                                              0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD__SHIFT                                                 0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ__SHIFT                                           0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT__SHIFT                                         0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET__SHIFT                                               0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15__SHIFT                                      0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__REQ_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RATE_MASK                                                  0x0006L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__WIDTH_MASK                                                 0x0018L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__PSTATE_MASK                                                0x0060L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__LPD_MASK                                                   0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__CDR_VCO_LOWFREQ_MASK                                       0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_AFE_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_DFE_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_REQ_MASK                                             0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__ADAPT_CONT_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__OFFCAN_CONT_MASK                                           0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESET_MASK                                                 0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN__RESERVED_15_15_MASK                                        0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7__SHIFT                                     0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__REF_LD_VAL_MASK                                          0x007FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_1__RESERVED_15_7_MASK                                       0xFF80L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13__SHIFT                                    0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__VCO_LD_VAL_MASK                                          0x1FFFL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_2__RESERVED_15_13_MASK                                      0xE000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN__SHIFT                                      0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_ATT_LVL_MASK                                          0x0007L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA1_GAIN_MASK                                        0x0078L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_VGA2_GAIN_MASK                                        0x0780L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_3__EQ_CTLE_BOOST_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11__SHIFT                                    0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_CTLE_POLE_MASK                                        0x0007L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__EQ_DFE_TAP1_MASK                                         0x07F8L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_IN_4__RESERVED_15_11_MASK                                      0xF800L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__ACK_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__EN_CTL_MASK                                              0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__ACK_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PCS_OUT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RX_ADAPT_ACK_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_ACK__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RX_ADAPT_FOM_MASK                                       0x00FFL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_ADAPT_FOM__RESERVED_15_8_MASK                                      0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RX_TXPRE_DIR_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPRE_DIR__RESERVED_15_2_MASK                                      0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RX_TXMAIN_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXMAIN_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RX_TXPOST_DIR_MASK                                     0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_TXPOST_DIR__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4__SHIFT                                     0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__LANE_NUMBER_MASK                                         0x000FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_LANE_NUMBER__RESERVED_15_4_MASK                                       0xFFF0L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_1__RESERVED_REG_1_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RESERVED_2__RESERVED_REG_2_MASK                                       0xFFFFL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL__SHIFT                             0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL__SHIFT                             0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN__SHIFT                              0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL__SHIFT                               0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN__SHIFT                                0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN__SHIFT                                0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN__SHIFT                           0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN__SHIFT                           0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL__SHIFT                           0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN__SHIFT                            0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_VAL_MASK                               0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_RESET_ATE_OVRD_EN_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_VAL_MASK                               0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_RESET_ATE_OVRD_EN_MASK                                0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_VAL_MASK                                 0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_REQ_ATE_OVRD_EN_MASK                                  0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_VAL_MASK                                 0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_REQ_ATE_OVRD_EN_MASK                                  0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_VAL_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_AFE_EN_OVRD_EN_MASK                             0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_VAL_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_ADAPT_DFE_EN_OVRD_EN_MASK                             0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_VAL_MASK                             0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__TX_DATA_EN_ATE_OVRD_EN_MASK                              0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_VAL_MASK                             0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_OVRD_IN__RX_DATA_EN_ATE_OVRD_EN_MASK                              0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN__SHIFT                 0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_VAL_MASK                  0x000FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RX_EQ_DELTA_IQ_OVRD_EN_MASK                   0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN__RESERVED_15_5_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL__SHIFT                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN__SHIFT                   0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL__SHIFT                  0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN__SHIFT                   0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_VAL_MASK                    0x0007L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RX_TERM_CTRL_OVRD_EN_MASK                     0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_VAL_MASK                    0x0070L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__TX_TERM_CTRL_OVRD_EN_MASK                     0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN__RESERVED_15_8_MASK                            0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6__SHIFT                               0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RX_TERM_CTRL_MASK                                  0x0007L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__TX_TERM_CTRL_MASK                                  0x0038L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TXRX_TERM_CTRL_IN__RESERVED_15_6_MASK                                 0xFFC0L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RX_CLK_EN_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_1__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL__SHIFT                        0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN__SHIFT                                 0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_AFE_GAIN_OVRD_VAL_MASK                         0x000FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_ATT_LVL_OVRD_VAL_MASK                          0x0070L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RX_EQ_OVRD_EN_MASK                                   0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_1__RESERVED_15_8_MASK                                   0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL__SHIFT                     0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13__SHIFT                                0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_DFE_TAP1_OVRD_VAL_MASK                         0x00FFL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RX_EQ_CTLE_BOOST_OVRD_VAL_MASK                       0x1F00L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_EQ_OVRD_IN_2__RESERVED_15_13_MASK                                  0xE000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL__SHIFT                               0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_ACK_VAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_VAL_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__PH2_CAL_REQ_OVRD_VAL_MASK                                 0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_PH2_CAL__RESERVED_15_3_MASK                                        0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK__SHIFT                                           0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR_MASK                                          0x0FFFL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN_MASK                                            0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START_MASK                                         0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN_MASK                                           0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_BREAK_MASK                                             0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR_MASK                                              0xFFFFL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__STATE_MASK                                                   0x001FL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY_MASK                                                 0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW_MASK                                               0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0_MASK                                             0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0_MASK                                            0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11_MASK                                          0xF800L
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__FAST_RX_AFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__FAST_RX_DFE_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__FAST_RX_BYPASS_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_BYPASS_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__FAST_RX_REFLVL_CAL_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_REFLVL_CAL__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL__SHIFT                                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__FAST_RX_IQ_CAL_MASK                                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_IQ_CAL__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__FAST_RX_AFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_AFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__FAST_RX_DFE_ADAPT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_DFE_ADAPT__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1_MASK                                             0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_MPLL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL__SHIFT                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__FAST_RX_CONT_DATA_CAL_MASK                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_DATA_CAL__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__FAST_RX_CONT_PHASE_CAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_PHASE_CAL__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__FAST_RX_CONT_AFE_CAL_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_RX_CONT_AFE_CAL__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL__SHIFT                                      0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL__SHIFT                                    0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2__SHIFT                                            0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL__SHIFT                                  0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL__SHIFT                                0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL__SHIFT                                 0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1__SHIFT                                            0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL__SHIFT                                       0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_DCC_CAL_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_DCC_CAL_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VPHUD_CAL_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_VREF_CAL_MASK                                        0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_SIGDET_CAL_MASK                                      0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_2_MASK                                              0x00E0L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_FAST_CONT_DCC_CAL_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_DCC_CAL_MASK                                    0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VPHUD_CAL_MASK                                  0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RX_FAST_CONT_VREF_CAL_MASK                                   0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__RESERVED_1_MASK                                              0x7000L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_FAST_FLAGS__TX_SKIP_SUP_CAL_MASK                                         0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK_MASK                                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK_MASK                                                0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2_MASK                                              0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE__SHIFT                                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV__SHIFT                                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RATE_MASK                                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__DIV_MASK                                                   0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__MPLL_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_FLAGS__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG__SHIFT                                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1__SHIFT                                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__FLAG_MASK                                                 0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_DCC_STATUS__RESERVED_15_1_MASK                                        0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN__SHIFT                                                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN__SHIFT                                                0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN__SHIFT                                                0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3__SHIFT                                               0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__PC_EN_MASK                                                         0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK1_EN_MASK                                                  0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__REG_BANK2_EN_MASK                                                  0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_OCLA__RESERVED_15_3_MASK                                                 0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__TX_EQ_UPDATE_FLAG_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_TX_EQ_UPDATE_FLAG__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_INIT_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__CMNCAL_RCAL_DONE_MASK                                0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_CMNCAL_RCAL_STATUS__RESERVED_15_2_MASK                                   0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RX_IQ_PHASE_OFFSET_MASK                              0x000FL
#define DPCSSYS_CR4_RAWLANEX_DIG_FSM_RX_IQ_PHASE_OFFSET__RESERVED_15_4_MASK                                   0xFFF0L
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR_MASK                                0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1_MASK                                  0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                          0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR_MASK                            0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1_MASK                             0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                                0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                                0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                    0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                              0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK__SHIFT                              0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK__SHIFT                        0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11__SHIFT                                      0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK_MASK                                  0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK_MASK                                  0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK_MASK                                      0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK_MASK                                0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_REQ_IRQ_MSK_MASK                                0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RX_PH2_CAL_DIS_IRQ_MSK_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__LANE_RX2TX_SER_LB_EN_IRQ_MSK_MASK                          0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__DCC_ONDMD_IRQ_MSK_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK__RESERVED_15_11_MASK                                        0xF800L
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_RESET_IRQ_MSK_MASK                                    0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__TX_REQ_IRQ_MSK_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_IRQ_MASK_2__RESERVED_15_2_MASK                                       0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RX_PH2_CAL_REQ_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ__SHIFT                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1__SHIFT                             0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RX_PH2_CAL_DIS_IRQ_MASK                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ__RESERVED_15_1_MASK                               0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RX_PH2_CAL_REQ_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_REQ_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR__SHIFT                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                         0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RX_PH2_CAL_DIS_IRQ_CLR_MASK                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_RX_PH2_CAL_DIS_IRQ_CLR__RESERVED_15_1_MASK                           0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ__SHIFT            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1__SHIFT                       0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__LANE_RX2TX_SER_LB_EN_IRQ_MASK              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ__RESERVED_15_1_MASK                         0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR__SHIFT    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                   0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__LANE_RX2TX_SER_LB_EN_IRQ_CLR_MASK      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_LANE_RX2TX_SER_LB_EN_IRQ_CLR__RESERVED_15_1_MASK                     0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__IRQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_DCC_ONDMD_IRQ__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                   0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__TX_RESET_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1_MASK                                     0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ__SHIFT                                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__TX_REQ_MASK                                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1_MASK                                       0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1_MASK                                   0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN__SHIFT                                 0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN__SHIFT                                     0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3__SHIFT                                    0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLA_EN_IN_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_MPLLB_EN_IN_MASK                                   0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__LANE_OVRD_EN_MASK                                       0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_IN__RESERVED_15_3_MASK                                      0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN__SHIFT                                    0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3__SHIFT                                   0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLA_EN_OUT_MASK                                 0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_MPLLB_EN_OUT_MASK                                 0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__LANE_OVRD_EN_MASK                                      0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_OVRD_OUT__RESERVED_15_3_MASK                                     0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE__SHIFT                                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3__SHIFT                                     0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLA_STATE_MASK                                         0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__MPLLB_STATE_MASK                                         0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__SUP_STATE_OVRD_EN_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_OVRD_IN__RESERVED_15_3_MASK                                       0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE__SHIFT                                        0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLA_STATE_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__MPLLB_STATE_MASK                                          0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL__SHIFT                             0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN__SHIFT                              0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL__SHIFT                          0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL__SHIFT                              0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN__SHIFT                               0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL__SHIFT                        0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN__SHIFT                         0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                     0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                      0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_VAL_MASK                               0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_BEACON_EN_OVRD_EN_MASK                                0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_VAL_MASK                            0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_DRV_EN_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_VAL_MASK                                0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_ASYNC_EN_OVRD_EN_MASK                                 0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_VAL_MASK                          0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_DWORD_CLK_SYNC_OVRD_EN_MASK                           0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                       0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                        0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_OVRD_OUT__TX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_TX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL__SHIFT                                 0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN__SHIFT                                  0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                     0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                      0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R__SHIFT                          0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8__SHIFT                                     0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_VAL_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_REQ_OVRD_EN_MASK                                      0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_VAL_MASK                                   0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_RESET_OVRD_EN_MASK                                    0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                       0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                        0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_VAL_R_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RX_PMA_DATA_EN_OVRD_EN_R_MASK                            0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_OVRD_OUT__RESERVED_15_8_MASK                                       0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK__SHIFT                                                 0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1__SHIFT                                       0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__ACK_MASK                                                   0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_PMA_IN__RESERVED_15_1_MASK                                         0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                                 0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                                  0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ_MASK                                   0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1_MASK                                    0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1__SHIFT                                    0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RTUNE_ACK_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_SUP_PMA_IN_1__RESERVED_15_1_MASK                                      0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R__SHIFT                            0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN__SHIFT                      0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN__SHIFT                          0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R__SHIFT                                 0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN__SHIFT                           0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN__SHIFT                          0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9__SHIFT                                    0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_R_MASK                              0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_WORD_CLK_OVRD_EN_MASK                        0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_R_MASK                                  0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_DATA_OVRD_EN_MASK                            0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_R_MASK                                   0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_PWM_CLK_OVRD_EN_MASK                             0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_R_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RX_PMA_TERM_CTL_OVRD_EN_MASK                            0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_IN__RESERVED_15_9_MASK                                      0xFE00L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN__SHIFT                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN__SHIFT                           0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL__SHIFT                              0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN__SHIFT                                 0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN__SHIFT                         0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7__SHIFT                                   0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_MASK                                     0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_EN_OVRD_EN_MASK                             0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_MASK                                0x000CL
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_PWM_CLK_SEL_OVRD_EN_MASK                        0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_MASK                                   0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RX_PMA_ASYNC_EN_OVRD_EN_MASK                           0x0040L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_MPHY_OVRD_OUT__RESERVED_15_7_MASK                                     0xFF80L
//DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL__SHIFT         0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN__SHIFT          0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8__SHIFT                               0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_VAL_MASK           0x007FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RX_PMA_IQ_PHASE_ADJUST_MAP_OVRD_EN_MASK            0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PMA_XF_RX_ADAPT_OVRD_OUT__RESERVED_15_8_MASK                                 0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                  0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                  0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                  0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_WAIT_MPLL_OFF_TIME_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P2_ALLOW_RXDET_MASK                                    0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P1_ALLOW_RXDET_MASK                                    0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0S_ALLOW_RXDET_MASK                                   0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__TX_P0_ALLOW_RXDET_MASK                                    0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_FSM_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN__SHIFT                                          0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL__SHIFT                                         0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME__SHIFT                             0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11__SHIFT                                     0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_EN_MASK                                            0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__TX_CLK_SEL_MASK                                           0x001EL
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__ASYNC_BEACON_WAIT_TIME_MASK                               0x07E0L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_CLK_CTL__RESERVED_15_11_MASK                                       0xF800L
//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_TX_DCC_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN__SHIFT                                                   0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1__SHIFT                                            0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__FSM_EN_MASK                                                     0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_OCLA__RESERVED_15_1_MASK                                              0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3__SHIFT                                       0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_TX_CTL_UPCS_OCLA__RESERVED_15_3_MASK                                         0xFFF8L
//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1__SHIFT                                     0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2__SHIFT                                      0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__EN_RX_CTL_FSM_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RATE_CHG_IN_P1_MASK                                       0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_FSM_CTL__RESERVED_15_2_MASK                                        0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT__SHIFT                               0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9__SHIFT                                 0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RX_LOS_MASK_CNT_MASK                                 0x01FFL
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_LOS_MASK_CTL__RESERVED_15_9_MASK                                   0xFE00L
//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT__SHIFT                       0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__RX_DATA_EN_OVRD_CNT_MASK                         0x001FL
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL__INT_REF_TRCK_CNT_MASK                            0xFFE0L
//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE_MASK                                       0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1_MASK                                0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE_MASK                                        0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1_MASK                                 0xFFFEL
//DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN__SHIFT                                             0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN__SHIFT                                              0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4__SHIFT                                       0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__DATA_EN_MASK                                               0x0007L
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__CLK_EN_MASK                                                0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_RX_CTL_UPCS_OCLA__RESERVED_15_4_MASK                                         0xFFF0L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL__SHIFT                                  0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL__SHIFT                                 0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN__SHIFT                                  0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL__SHIFT                                0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN__SHIFT                                 0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL__SHIFT                                   0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN__SHIFT                                    0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT                  0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                   0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13__SHIFT                                 0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_VAL_MASK                                    0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RATE_OVRD_EN_MASK                                     0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_VAL_MASK                                   0x0018L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__WIDTH_OVRD_EN_MASK                                    0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_VAL_MASK                                  0x00C0L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__PSTATE_OVRD_EN_MASK                                   0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_VAL_MASK                                     0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LPD_OVRD_EN_MASK                                      0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_VAL_MASK                    0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__LANE_RX2TX_PAR_LB_EN_OVRD_EN_MASK                     0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN__RESERVED_15_13_MASK                                   0xE000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE__SHIFT                                         0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD__SHIFT                                            0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH__SHIFT                                          0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE__SHIFT                                           0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL__SHIFT                                      0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN__SHIFT                                        0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN__SHIFT                                        0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE__SHIFT                               0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE__SHIFT                               0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN__SHIFT                              0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL__SHIFT                            0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN__SHIFT                             0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__PSTATE_MASK                                           0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__LPD_MASK                                              0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__WIDTH_MASK                                            0x0018L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__RATE_MASK                                             0x00E0L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLLB_SEL_MASK                                        0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MPLL_EN_MASK                                          0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__OVRD_EN_MASK                                          0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLA_STATE_MASK                                 0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLLB_STATE_MASK                                 0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__MSTR_MPLL_OVRD_EN_MASK                                0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_VAL_MASK                              0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN__TX_ASYNC_EN_OVR_EN_MASK                               0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL__SHIFT                           0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN__SHIFT                            0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL__SHIFT                           0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN__SHIFT                            0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL__SHIFT                          0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN__SHIFT                           0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL__SHIFT                         0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN__SHIFT                          0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                 0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL__SHIFT                       0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN__SHIFT                        0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15__SHIFT                               0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_VAL_MASK                             0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__DETRX_REQ_OVRD_EN_MASK                              0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_VAL_MASK                             0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__VBOOST_EN_OVRD_EN_MASK                              0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_VAL_MASK                            0x00F0L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__IBOOST_LVL_OVRD_EN_MASK                             0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_VAL_MASK                           0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_BEACON_EN_OVR_EN_MASK                            0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                  0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                   0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_VAL_MASK                         0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__TX_ASYNC_DATA_OVRD_EN_MASK                          0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_TX_OVRD_IN_1__RESERVED_15_15_MASK                                 0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN__SHIFT                                0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2__SHIFT                                0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLB_LOOP_EN_MASK                                  0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__MPLLA_LOOP_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_MASTER_MPLL_LOOP__RESERVED_15_2_MASK                                  0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED__SHIFT                                     0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL__SHIFT                      0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN__SHIFT                       0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL__SHIFT                      0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN__SHIFT                       0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ__SHIFT                                    0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                            0x9
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT__SHIFT                                   0xa
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT__SHIFT                                  0xb
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN__SHIFT                                 0xc
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13__SHIFT                               0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_MASK                                       0x0003L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_VAL_MASK                        0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_LFPS_EN_OVRD_EN_MASK                         0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_VAL_MASK                        0x0070L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RX_LOS_THRSHLD_OVRD_EN_MASK                         0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_MASK                                      0x0100L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_REQ_OVRD_EN_MASK                              0x0200L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__ADAPT_CONT_MASK                                     0x0400L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__OFFCAN_CONT_MASK                                    0x0800L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__CONT_OVRD_EN_MASK                                   0x1000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_1__RESERVED_15_13_MASK                                 0xE000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                           0xd
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD__SHIFT                         0xe
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN__SHIFT                      0xf
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_MASK                                0x1FFFL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN_MASK                             0x2000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_MASK                           0x4000L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_2__VCO_LOWFREQ_VAL_OVRD_EN_MASK                        0x8000L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD__SHIFT                              0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN__SHIFT                           0x7
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8__SHIFT                                0x8
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_MASK                                0x007FL
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__REF_LD_VAL_OVRD_EN_MASK                             0x0080L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_ATE_RX_OVRD_IN_3__RESERVED_15_8_MASK                                  0xFF00L
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID__SHIFT                                        0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN__SHIFT                                0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2__SHIFT                                   0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_MASK                                          0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RX_VALID_OVRD_EN_MASK                                  0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_RX_OVRD_OUT_2__RESERVED_15_2_MASK                                     0xFFFCL
//DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL__SHIFT                    0x0
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                     0x1
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R__SHIFT                            0x2
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R__SHIFT                             0x3
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R__SHIFT                         0x4
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R__SHIFT                          0x5
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6__SHIFT                                    0x6
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_VAL_MASK                      0x0001L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__LANE_TX2RX_SER_LB_EN_OVRD_EN_MASK                       0x0002L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_VAL_R_MASK                              0x0004L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_DATA_EN_OVRD_EN_R_MASK                               0x0008L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_VAL_R_MASK                           0x0010L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__TX_ASYNC_DATA_OVRD_EN_R_MASK                            0x0020L
#define DPCSSYS_CR4_RAWLANEX_DIG_PCS_XF_TX_OVRD_IN_2__RESERVED_15_6_MASK                                      0xFFC0L


// addressBlock: c20_phy_cr0_rdpcspipecrind
//C20_PHY_CR0_SUP_DIG_IDCODE_LO
#define C20_PHY_CR0_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
//C20_PHY_CR0_SUP_DIG_IDCODE_HI
#define C20_PHY_CR0_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
//C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
#define C20_PHY_CR0_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
#define C20_PHY_CR0_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
//C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
//C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
//C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
//C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
#define C20_PHY_CR0_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
//C20_PHY_CR0_SUP_DIG_DEBUG
#define C20_PHY_CR0_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define C20_PHY_CR0_SUP_DIG_DEBUG__RESERVED_15_3__SHIFT                                                       0x3
//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
//C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
//C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
//C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
#define C20_PHY_CR0_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
//C20_PHY_CR0_SUP_DIG_ASIC_IN_0
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
//C20_PHY_CR0_SUP_DIG_ASIC_IN_1
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
#define C20_PHY_CR0_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
//C20_PHY_CR0_SUP_DIG_ASIC_OUT_0
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
#define C20_PHY_CR0_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
//C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
#define C20_PHY_CR0_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
//C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
#define C20_PHY_CR0_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
//C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
#define C20_PHY_CR0_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
#define C20_PHY_CR0_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
//C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
//C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG
#define C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define C20_PHY_CR0_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG
#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
#define C20_PHY_CR0_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
//C20_PHY_CR0_SUP_DIG_RTUNE_STAT
#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
#define C20_PHY_CR0_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
//C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL
#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT
#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
//C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
//C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1
#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
//C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS
#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
#define C20_PHY_CR0_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define C20_PHY_CR0_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
#define C20_PHY_CR0_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
//C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
//C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
//C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_7_7__SHIFT                                        0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_12_11__SHIFT                                      0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_0__SHIFT                                0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_1__SHIFT                                0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_2__SHIFT                                0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_3__SHIFT                                0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_4__SHIFT                                0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_5__SHIFT                                0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6__SHIFT                                0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_TX_RBOOST_EN__SHIFT                             0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_6__SHIFT                                        0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_11_8__SHIFT                                       0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_15_12__SHIFT                                      0xc
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_1_0__SHIFT                                        0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_3_2__SHIFT                                        0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_5_4__SHIFT                                        0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_7_6__SHIFT                                        0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_OVERRIDE_RING_CNTRL__SHIFT                     0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_0__SHIFT                               0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_1__SHIFT                               0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_2__SHIFT                               0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_3__SHIFT                               0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_4__SHIFT                               0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_5__SHIFT                               0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_6__SHIFT                               0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_7__SHIFT                               0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_8__SHIFT                               0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_9__SHIFT                               0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_10__SHIFT                              0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_11__SHIFT                              0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_12__SHIFT                              0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_13__SHIFT                              0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_14__SHIFT                              0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_15__SHIFT                              0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_16__SHIFT                              0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_17__SHIFT                              0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_18__SHIFT                              0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_19__SHIFT                              0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_20__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21__SHIFT                              0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_22__SHIFT                              0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_23__SHIFT                              0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_24__SHIFT                              0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_25__SHIFT                              0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_26__SHIFT                              0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_27__SHIFT                              0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28__SHIFT                              0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__RESERVED_12_12__SHIFT                                    0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_VREG_OVERRIDE_RING_CNTRL__SHIFT                    0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_PMIX_DLL_BYOAZ__SHIFT                              0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_2_0__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_DSQ_EN__SHIFT                                      0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_PFD__SHIFT                              0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_S__SHIFT                                0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_CP__SHIFT                               0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_PMIX__SHIFT                             0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_RIGHT__SHIFT                            0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_LEFT__SHIFT                             0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_CLK_BYPASS__SHIFT                                   0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_RIGHT_BYPASS__SHIFT                                 0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_LEFT_BYPASS__SHIFT                                  0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_CP_BYPASS__SHIFT                                    0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_PFD_BYPASS__SHIFT                                   0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREF_VMARG__SHIFT                          0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_OVERFLOW__SHIFT                           0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_MPLL_RESERVED__SHIFT                      0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_STANDBY_MODE__SHIFT                        0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_LEG_SR_CON__SHIFT                          0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_SPO_SPEED_OVERRIDE__SHIFT                      0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_DIV_SPO__SHIFT                            0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_BYPASS_EN__SHIFT                       0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_EN_COUNT__SHIFT                            0xb
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DOUBLER_GAIN__SHIFT                        0x9
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_VREF_VMARG__SHIFT                          0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL__SHIFT                                 0xe
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DSQ__SHIFT                                 0xf
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
//C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
#define C20_PHY_CR0_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
//C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
//C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
//C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM
#define C20_PHY_CR0_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLL_IN
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
//C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE
#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
//C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS
#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS
#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
#define C20_PHY_CR0_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1
#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
#define C20_PHY_CR0_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
//C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION
#define C20_PHY_CR0_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
#define C20_PHY_CR0_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL
#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
#define C20_PHY_CR0_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_0
#define C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_0__VAL__SHIFT                                                        0x0
//C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_1
#define C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_1__VAL__SHIFT                                                        0x0
//C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_2
#define C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_2__VAL__SHIFT                                                        0x0
//C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_3
#define C20_PHY_CR0_RAWCMN_DIG_CMN_DEBUG_3__VAL__SHIFT                                                        0x0
//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
//C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
#define C20_PHY_CR0_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9
#define C20_PHY_CR0_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
//C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
#define C20_PHY_CR0_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION
#define C20_PHY_CR0_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
//C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1
#define C20_PHY_CR0_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
//C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
#define C20_PHY_CR0_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION
#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
//C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR
#define C20_PHY_CR0_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR0_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR0_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL
#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL
#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR
#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR0_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR0_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR0_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR0_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR0_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL
#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL
#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR
#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR0_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR0_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR0_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR0_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR0_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL
#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL
#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR
#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR0_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR0_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR0_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR0_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR0_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL
#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR0_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL
#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR
#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR0_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR0_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR0_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR0_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR0_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR0_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR0_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR0_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR0_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL
#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR0_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR0_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL
#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR
#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR0_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR0_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR0_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR0_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR0_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2


// addressBlock: c20_phy_lane0_pipe0_rdpcspipemsgbusind
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS__DEBUG_INFO_ADDRESS__SHIFT               0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE__DEBUG_INFO_VALUE__SHIFT                   0x0
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
//C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
#define C20_PHY_LANE0_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2


// addressBlock: c20_phy_lane1_pipe0_rdpcspipemsgbusind
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS__DEBUG_INFO_ADDRESS__SHIFT               0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE__DEBUG_INFO_VALUE__SHIFT                   0x0
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
//C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
#define C20_PHY_LANE1_PIPE0_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2


// addressBlock: c20_phy_cr1_rdpcspipecrind
//C20_PHY_CR1_SUP_DIG_IDCODE_LO
#define C20_PHY_CR1_SUP_DIG_IDCODE_LO__VAL__SHIFT                                                             0x0
//C20_PHY_CR1_SUP_DIG_IDCODE_HI
#define C20_PHY_CR1_SUP_DIG_IDCODE_HI__VAL__SHIFT                                                             0x0
//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN__SHIFT                                               0x0
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_EN_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN__SHIFT                                          0x2
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_DIV2_EN_OVRD_EN__SHIFT                                  0x3
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD__SHIFT                                              0x4
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_USE_PAD_OVRD_EN__SHIFT                                      0x5
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE__SHIFT                                            0x6
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__REF_CLK_RANGE_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN__SHIFT                                                    0xa
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__BG_EN_OVRD_EN__SHIFT                                            0xb
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD__SHIFT                                  0xc
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__MPLL_SHORT_LOCK_EN_OVRD_EN__SHIFT                               0xd
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_0__RESERVED_15_14__SHIFT                                           0xe
//C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL__SHIFT                                          0x0
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VPH_SEL_OVRD_EN__SHIFT                                  0x2
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL__SHIFT                                           0x3
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__NOMINAL_VP_SEL_OVRD_EN__SHIFT                                   0x5
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN__SHIFT                                            0x6
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_CLKDET_EN_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL__SHIFT                                       0x8
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                               0x9
#define C20_PHY_CR1_SUP_DIG_REFCLK_OVRD_IN_1__RESERVED_15_10__SHIFT                                           0xa
//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__MPLLA_DIV_OVRD_EN__SHIFT                                   0x9
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__MPLLB_DIV_OVRD_EN__SHIFT                                   0x9
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                                     0x0
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_PIXEL_CLK_DIV_OVRD_EN__SHIFT                             0x2
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV__SHIFT                                               0x3
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__MPLLB_HDMI_DIV_OVRD_EN__SHIFT                                       0x6
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE__SHIFT                                              0x7
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_SUP_DIG_HDMI_OVRD_IN__RESERVED_15_9__SHIFT                                                0x9
//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_EN_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x2
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x8
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x9
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xc
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xd
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xe
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_0__MPLLA_OVRD_EN__SHIFT                                             0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_BW_OVRD_EN__SHIFT                                          0xe
#define C20_PHY_CR1_SUP_DIG_MPLLA_OVRD_IN_1__MPLLA_LC_FREQSEL__SHIFT                                          0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_OVRD_IN__MPLLA_BW_LOW__SHIFT                                         0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_OVRD_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_EN__SHIFT                                          0x2
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x3
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_OVRD_EN__SHIFT                                     0x4
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x5
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0xd
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__MPLLA_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_OVRD_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_EN_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_VAL__SHIFT                               0x5
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_WORD_CLK_DIV_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_VAL__SHIFT                                 0x8
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_TX_CLK_DIV_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__MPLLB_OVRD_EN__SHIFT                                             0xc
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_0__RESERVED_15_13__SHIFT                                            0xd
//C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_OVRD_IN_1__RESERVED_15_12__SHIFT                                            0xc
//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_GS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT__SHIFT                                          0x8
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_0__MPLLB_CP_INT_OVRD_EN__SHIFT                                  0xf
//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_GS_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP__SHIFT                                         0x8
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_1__MPLLB_CP_PROP_OVRD_EN__SHIFT                                 0xf
//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I__SHIFT                                             0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_V2I_OVRD_EN__SHIFT                                     0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x3
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__MPLLB_FREQ_VCO_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_OVRD_IN_2__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_EN__SHIFT                                          0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x3
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_OVRD_EN__SHIFT                                     0x4
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x5
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0xa
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_CFG_UPDATE_EN_CLEAR_DIS__SHIFT                    0xc
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0xd
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__MPLLB_FRAC_ATOMIC_MODE_OVRD_EN__SHIFT                        0xe
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_OVRD_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_REQ__SHIFT                                                   0x0
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RTUNE_OVRD_EN__SHIFT                                               0x1
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_REQ_IN__SHIFT                                                  0x2
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_ACK_IN__SHIFT                                                  0x3
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RES_OVRD_EN__SHIFT                                                 0x4
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN__SHIFT                                          0x5
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__TEST_TX_REF_CLK_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_0__RESERVED_15_7__SHIFT                                               0x7
//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET__SHIFT                                            0x0
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__TXUP_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET__SHIFT                                              0xa
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_1__RX_TERM_OFFSET_OVRD_EN__SHIFT                                      0xf
//C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET__SHIFT                                            0x0
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__TXDN_TERM_OFFSET_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_IN_2__RESERVED_15_10__SHIFT                                              0xa
//C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK__SHIFT                                                    0x0
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RTUNE_ACK_OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT__SHIFT                                                  0x2
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_REQ_OUT_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT__SHIFT                                                  0x4
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RES_ACK_OUT_OVRD_EN__SHIFT                                          0x5
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE__SHIFT                                                  0x6
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLA_STATE_OVRD_EN__SHIFT                                          0x7
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE__SHIFT                                                  0x8
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__MPLLB_STATE_OVRD_EN__SHIFT                                          0x9
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD__SHIFT                                           0xa
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_LANE_STATE_OVRD_EN__SHIFT                                        0xb
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD__SHIFT                                            0xc
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__BG_SUP_STATE_OVRD_EN__SHIFT                                         0xd
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_OUT__RESERVED_15_14__SHIFT                                               0xe
//C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RX_VREF_CTRL_OVRD_EN__SHIFT                                          0x5
#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL__SHIFT                                                 0x6
#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__TX_VBOOST_LVL_OVRD_EN__SHIFT                                         0x9
#define C20_PHY_CR1_SUP_DIG_LVL_OVRD_IN__RESERVED_15_10__SHIFT                                                0xa
//C20_PHY_CR1_SUP_DIG_DEBUG
#define C20_PHY_CR1_SUP_DIG_DEBUG__DTB_SEL__SHIFT                                                             0x0
#define C20_PHY_CR1_SUP_DIG_DEBUG__RESERVED_15_3__SHIFT                                                       0x3
//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_EN__SHIFT                                                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__REF_CLK_MPLLA_DIV__SHIFT                                         0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_WORD_CLK_DIV__SHIFT                                        0x4
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_DIV16P5_CLK_EN__SHIFT                                      0x6
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_TX_CLK_DIV__SHIFT                                          0x7
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_FB_CLK_DIV4_EN__SHIFT                                      0xa
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_CTL_BUF_BYPASS__SHIFT                                      0xb
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__MPLLA_BW_THRESHOLD__SHIFT                                        0xc
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_0__RESERVED_15_14__SHIFT                                            0xe
//C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__MPLLA_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
//C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_LOW_ASIC_IN__MPLLA_BW_LOW__SHIFT                                         0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_MPLLA_BW_HIGH_ASIC_IN__MPLLA_BW_HIGH__SHIFT                                       0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_EN__SHIFT                                          0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_UP_SPREAD__SHIFT                                   0x2
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_SSC_STEP_SIZE_20_16__SHIFT                             0x3
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__MPLLA_FRAC_ATOMIC_MODE__SHIFT                                0x9
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_1__MPLLA_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__MPLLA_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_3__MPLLA_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_4__MPLLA_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_5__MPLLA_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_ASIC_IN_6__MPLLA_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_EN__SHIFT                                                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__REF_CLK_MPLLB_DIV__SHIFT                                         0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_WORD_CLK_DIV__SHIFT                                        0x4
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__MPLLB_TX_CLK_DIV__SHIFT                                          0x6
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_0__RESERVED_15_9__SHIFT                                             0x9
//C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__MPLLB_MULTIPLIER__SHIFT                                          0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_ASIC_IN_1__RESERVED_15_12__SHIFT                                            0xc
//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT_GS__SHIFT                                       0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__MPLLB_CP_INT__SHIFT                                          0x7
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_0__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP_GS__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__MPLLB_CP_PROP__SHIFT                                         0x7
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_1__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_V2I__SHIFT                                             0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__MPLLB_FREQ_VCO__SHIFT                                        0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_VCO_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_EN__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_EN__SHIFT                                          0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_UP_SPREAD__SHIFT                                   0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_SSC_STEP_SIZE_20_16__SHIFT                             0x3
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                              0x8
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__MPLLB_FRAC_ATOMIC_MODE__SHIFT                                0x9
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_0__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_1__MPLLB_SSC_STEP_SIZE_15_0__SHIFT                              0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__MPLLB_SSC_PEAK_19_16__SHIFT                                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_2__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_3__MPLLB_SSC_PEAK_15_0__SHIFT                                   0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_4__MPLLB_FRAC_QUOT__SHIFT                                       0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_5__MPLLB_FRAC_DEN__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_ASIC_IN_6__MPLLB_FRAC_REM__SHIFT                                        0x0
//C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__MPLLA_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_DIV_CLK_ASIC_IN__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_CLK_EN__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_DIV_MULTIPLIER__SHIFT                                0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT                            0x9
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__MPLLB_HDMI_DIV__SHIFT                                      0xb
#define C20_PHY_CR1_SUP_DIG_MPLLB_DIV_CLK_ASIC_IN__RESERVED_15_14__SHIFT                                      0xe
//C20_PHY_CR1_SUP_DIG_ASIC_IN_0
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__PHY_RESET__SHIFT                                                       0x0
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_EN__SHIFT                                                      0x1
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_CLK_DIV2_EN__SHIFT                                                 0x2
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_USE_PAD__SHIFT                                                     0x3
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_BURNIN__SHIFT                                                     0x4
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__TEST_POWERDOWN__SHIFT                                                  0x5
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RTUNE_REQ__SHIFT                                                       0x6
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_REQ_IN__SHIFT                                                      0x7
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RES_ACK_IN__SHIFT                                                      0x8
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__BG_EN__SHIFT                                                           0x9
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                              0xa
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__REF_RANGE__SHIFT                                                       0xb
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__HDMIMODE_ENABLE__SHIFT                                                 0xe
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_0__RESERVED_15_15__SHIFT                                                  0xf
//C20_PHY_CR1_SUP_DIG_ASIC_IN_1
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__SUP_MISC__SHIFT                                                        0x0
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_STOP_CLK_EN__SHIFT                                                0x8
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__TEST_TX_REF_CLK_EN__SHIFT                                              0x9
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VPH_SEL__SHIFT                                                 0xa
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__NOMINAL_VP_SEL__SHIFT                                                  0xc
#define C20_PHY_CR1_SUP_DIG_ASIC_IN_1__RESERVED_15_14__SHIFT                                                  0xe
//C20_PHY_CR1_SUP_DIG_ASIC_OUT_0
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__REF_CLKDET_RESULT__SHIFT                                              0x0
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLA_STATE__SHIFT                                                    0x1
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__MPLLB_STATE__SHIFT                                                    0x2
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RTUNE_ACK__SHIFT                                                      0x3
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_REQ_OUT__SHIFT                                                    0x4
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RES_ACK_OUT__SHIFT                                                    0x5
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__DTB_OUT__SHIFT                                                        0x6
#define C20_PHY_CR1_SUP_DIG_ASIC_OUT_0__RESERVED_15_8__SHIFT                                                  0x8
//C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_VREF_CTRL__SHIFT                                                  0x0
#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__TX_VBOOST_LVL__SHIFT                                                 0x5
#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__REF_CLKDET_EN__SHIFT                                                 0x8
#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RX_TERM_OFFSET__SHIFT                                                0x9
#define C20_PHY_CR1_SUP_DIG_LVL_ASIC_IN__RESERVED_15_14__SHIFT                                                0xe
//C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_VAL__SHIFT                                           0x0
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__SUP_MISC_OVRD_EN__SHIFT                                            0x8
#define C20_PHY_CR1_SUP_DIG_SUP_OVRD_MISC__RESERVED_15_9__SHIFT                                               0x9
//C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__TXUP_TERM_OFFSET__SHIFT                                 0x0
#define C20_PHY_CR1_SUP_DIG_TXUP_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__TXDN_TERM_OFFSET__SHIFT                                 0x0
#define C20_PHY_CR1_SUP_DIG_TXDN_TERM_OFFSET_ASIC_IN__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_VAL__SHIFT                                0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_VAL__SHIFT                                  0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_STANDBY_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_VAL__SHIFT                             0x4
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__MPLLB_CAL_DAC_CODE_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_OVRD_IN__RESERVED_15_10__SHIFT                                          0xa
//C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_FORCE__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_STANDBY__SHIFT                                           0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__MPLLB_CAL_DAC_CODE__SHIFT                                      0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_CAL_ASIC_IN__RESERVED_15_7__SHIFT                                           0x7
//C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG
#define C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG__FLIP_COMP__SHIFT                                                     0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG__MAN_TUNE__SHIFT                                                      0x1
#define C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG__SET_VAL__SHIFT                                                       0x2
#define C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG__TYPE__SHIFT                                                          0x3
#define C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG__VALUE__SHIFT                                                         0x5
#define C20_PHY_CR1_SUP_DIG_RTUNE_DEBUG__TXUP_GO__SHIFT                                                       0xf
//C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG
#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RX_CAL_EN__SHIFT                                                    0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED__SHIFT                                                     0x1
#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TX_CAL_EN__SHIFT                                                    0x2
#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__SUP_ANA_TERM_CTRL__SHIFT                                            0x3
#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__TXUP_TXDN_SEL__SHIFT                                                0x6
#define C20_PHY_CR1_SUP_DIG_RTUNE_CONFIG__RESERVED_15_7__SHIFT                                                0x7
//C20_PHY_CR1_SUP_DIG_RTUNE_STAT
#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__STAT__SHIFT                                                           0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_STATE__SHIFT                                                    0xa
#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RTUNE_ANA_MODE__SHIFT                                                 0xd
#define C20_PHY_CR1_SUP_DIG_RTUNE_STAT__RESERVED_15_15__SHIFT                                                 0xf
//C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL
#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RX_SET_VAL__SHIFT                                               0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_SET_VAL__RESERVED_15_6__SHIFT                                            0x6
//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__TXDN_SET_VAL__SHIFT                                           0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__TXUP_SET_VAL__SHIFT                                           0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_SET_VAL__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT
#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RX_STAT__SHIFT                                                     0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_RX_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__TXDN_STAT__SHIFT                                                 0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXDN_STAT__RESERVED_15_10__SHIFT                                            0xa
//C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__TXUP_STAT__SHIFT                                                 0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TXUP_STAT__RESERVED_15_10__SHIFT                                            0xa
//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__AVG__SHIFT                                                  0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_0__RESERVED_15_10__SHIFT                                       0xa
//C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1
#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__UPDN__SHIFT                                                 0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_TX_TERM_CODE_1__RESERVED_15_10__SHIFT                                       0xa
//C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS
#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__FAST_RTUNE__SHIFT                                               0x0
#define C20_PHY_CR1_SUP_DIG_RTUNE_FAST_FLAGS__RESERVED_15_1__SHIFT                                            0x1
//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_SUP_EN_TIME__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__FAST_BG_WAIT__SHIFT                                      0x9
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__BG_FSM_RETRIGGER__SHIFT                                  0xa
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_0__RESERVED_15_11__SHIFT                                    0xb
//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__BG_LANE_EN_TIME__SHIFT                                   0x0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_1__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__BG_KICK_START_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_PWRUP_TIME_2__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__REF_VREG_FAST_START_TIME__SHIFT                         0x0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__FAST_REF_WAIT__SHIFT                                    0x5
#define C20_PHY_CR1_SUP_DIG_CLK_RST_REF_PWRUP_TIME_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_SUP_STATE__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_LANE_STATE__SHIFT                                     0x1
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__REF_FSM_STATE__SHIFT                                     0x2
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__BG_FSM_STATE__SHIFT                                      0x4
#define C20_PHY_CR1_SUP_DIG_CLK_RST_BG_STATE_STATUS__RESERVED_15_6__SHIFT                                     0x6
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__LOAD_CNT__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_SKIPCAL__SHIFT                                0x4
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__MPLL_EXTCAL__SHIFT                                 0x5
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CHKFRQ_EN__SHIFT                               0x6
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_COARSE_TUNE__SHIFT                             0x7
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_0__EXT_CAL_DONE__SHIFT                                0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__EXT_FINE_TUNE__SHIFT                               0xa
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_14__SHIFT                              0xe
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_TOOSLOW__SHIFT                                      0x4
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__CHKFRQ_DONE__SHIFT                                       0x5
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL_RDY__SHIFT                                      0x6
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x7
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x8
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x9
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0xa
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0xb
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0xc
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xd
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xe
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT__MPLL_ANA_VREG_SPEEDUP__SHIFT                             0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__VCO_STABILIZATION_TIME__SHIFT               0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__MPLL_CAL_UPDATE_TIME__SHIFT                 0xa
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__VCO_CLK_STABILIZATION_TIME__SHIFT           0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PCLK_EN_TIME__SHIFT                         0xb
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_DIS_TIME__SHIFT                        0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VCO_PWRDN_TIME__SHIFT                  0x5
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_2__MPLL_VREG_SPEEDUP_TIME__SHIFT               0xa
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_ANA_PWRUP_TIME__SHIFT                  0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__MPLL_FBDIGCLK_EN_TIME__SHIFT                0x7
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_COARSE_TUNE_VAL__SHIFT                     0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__MPLL_FINE_TUNE_VAL__SHIFT                       0x8
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_TUNE_VAL__RESERVED_15_12__SHIFT                           0xc
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_COARSE_TUNE__SHIFT             0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_PROP__SHIFT          0x8
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__MPLL_SKIPCAL_FINE_TUNE_INTEG__SHIFT         0xa
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_TUNE__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_START_0__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_0__COARSE_LIMIT_0__SHIFT                      0x8
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_START_1__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_1__COARSE_LIMIT_1__SHIFT                      0x8
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_START_2__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_2__COARSE_LIMIT_2__SHIFT                      0x8
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_START_3__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWR_FSM_CFG_3__COARSE_LIMIT_3__SHIFT                      0x8
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__VCO_STABILIZATION_SHORT_TIME__SHIFT         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_FBCLK_EN_TIME__SHIFT                   0xa
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__VCO_CLK_STABILIZATION_SHORT_TIME__SHIFT     0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_5__RESERVED_15_11__SHIFT                       0xb
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__VCO_GEARSHIFT_LONG_TIME__SHIFT              0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_6__RESERVED_15_10__SHIFT                       0xa
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__VCO_GEARSHIFT_SHORT_TIME__SHIFT             0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_7__RESERVED_15_10__SHIFT                       0xa
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_PWRUP_TIME_8__RESERVED_15_7__SHIFT                        0x7
//C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_RSTR_TUNE_CODE_OVRD_EN__SHIFT                 0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__MPLL_SKIP_CAL_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_2__RESERVED_15_2__SHIFT                               0x2
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_SUP_DIG_MPLLA_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_VAL__SHIFT                           0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MPLL_CAL_OVRD_EN__SHIFT                            0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__MAX_RANGE__SHIFT                                   0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__OVRD_SEL__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_FBDIGCLK_EN__SHIFT                            0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__MPLL_PCLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_PWRUP__SHIFT                             0x3
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__FAST_MPLL_LOCK__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_CAL_CTRL_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__FSM_STATE__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES__SHIFT                                      0x4
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES__SHIFT                                      0x5
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_PCLK_EN__SHIFT                                      0x6
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_OUTPUT_EN__SHIFT                                    0x7
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_FBCLK_EN__SHIFT                                     0x8
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_CAL__SHIFT                                          0x9
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_RST__SHIFT                                          0xa
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_ANA_EN__SHIFT                                       0xb
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_LOCK__SHIFT                                         0xc
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_R_LANES_SYNC__SHIFT                                 0xd
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__MPLL_L_LANES_SYNC__SHIFT                                 0xe
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_STAT__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__LOCK_TIME__SHIFT                            0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__STABLE_TIME__SHIFT                          0x8
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_0__RESERVED_15_14__SHIFT                       0xe
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__GEARSHIFT_TIME__SHIFT                       0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_1__PRESET_TIME__SHIFT                          0x8
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PWRDN_WAIT_TIME__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__PCLK_EN_TIME__SHIFT                         0x6
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_2__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PCLK_DIS_TIME__SHIFT                        0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__PWRDN_TIME__SHIFT                           0x6
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_3__RESERVED_15_12__SHIFT                       0xc
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__MPLL_ANA_DAC_STATUS__SHIFT                0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_ANA_DAC_STATUS__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__MPLL_OUTPUT_DELAY_TIME__SHIFT               0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_UPLL_PWR_CTL_MPLL_PWRUP_TIME_4__RESERVED_15_7__SHIFT                        0x7
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_FRAC_OUT__FRAC_OUT_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_SSC_RAMP__SSC_RAMP_OVRD_EN__SHIFT                                       0xf
//C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__BYPASS_MPLL_LOGIC__SHIFT                                        0x0
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__SSC_FRAC_CLK_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_SUP_DIG_MPLLB_SSC_CONFIG__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RT_ANA_COMP_RESULT__SHIFT                                         0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_CLKDET_RESULT__SHIFT                                      0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_LOCK__SHIFT                                             0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_EOC__SHIFT                                              0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__MPLLB_ANA_DAC_OUT__SHIFT                                          0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__REF_ANA_DCO_CLKCAL__SHIFT                                         0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_IN__RESERVED_15_10__SHIFT                                             0xa
//C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_EN__SHIFT                                                 0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_VREF_FAST_START__SHIFT                                    0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__BG_ANA_KICK_START_EN__SHIFT                                      0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_CLK_EN__SHIFT                                            0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_REF_SEL__SHIFT                                      0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__REF_ANA_VREG_FAST_START__SHIFT                                   0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_TERM_CTRL__SHIFT                                         0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_EN__SHIFT                                                 0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_COMP_RST__SHIFT                                           0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__RT_ANA_MODE__SHIFT                                               0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__SUP_ANA_FLYOVER_EN__SHIFT                                        0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_STAT_OUT__ANA_ASYNC_RST__SHIFT                                             0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_EN__SHIFT                                        0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_VREG_SPEEDUP__SHIFT                              0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_FB_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_CAL__SHIFT                                       0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_RST__SHIFT                                       0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_GEARSHIFT__SHIFT                                 0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_EN__SHIFT                                 0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_PMIX_EN__SHIFT                                   0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_L_EN__SHIFT                               0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_OUTPUT_R_EN__SHIFT                               0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV_CLK_EN__SHIFT                                0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__MPLLA_ANA_DIV16P5_CLK_EN__SHIFT                            0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_STAT_OUT__RESERVED_15_12__SHIFT                                      0xc
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_EN__SHIFT                                        0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_FB_CLK_EN__SHIFT                                 0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL__SHIFT                                       0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_RST__SHIFT                                       0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_GEARSHIFT__SHIFT                                 0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_EN__SHIFT                                 0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_PMIX_EN__SHIFT                                   0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_L_EN__SHIFT                               0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_OUTPUT_R_EN__SHIFT                               0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_WORD_CLK_EN__SHIFT                               0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_DIV_CLK_EN__SHIFT                                0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_HDMI_DIV_CLK_EN__SHIFT                           0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_CAL_FORCE__SHIFT                                 0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__MPLLB_ANA_STANDBY__SHIFT                                   0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_STAT_OUT__RESERVED_15_14__SHIFT                                      0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN__SHIFT                                                  0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_EN_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START__SHIFT                                          0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_FAST_START_OVRD_EN__SHIFT                                  0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START__SHIFT                                          0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_KICK_START_OVRD_EN__SHIFT                                  0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_SHUFFLER__SHIFT                                0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__BG_ANA_DISABLE_CHOP_AMP__SHIFT                                0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST__SHIFT                                          0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__ANA_ASYNC_RST_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_BG_OVRD_OUT__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_CLK_EN_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL__SHIFT                                      0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_REF_SEL_OVRD_EN__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START__SHIFT                                   0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_VREG_FAST_START_OVRD_EN__SHIFT                           0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_RANGE__SHIFT                                     0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__REF_ANA_DCO_FINETUNE__SHIFT                                  0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_REF_OVRD_OUT__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__REF_ANA_CLKINT_SEL__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_CAL_VREF_SEL__SHIFT                                   0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RX_ANA_VCO_TC_VREF_SEL__SHIFT                                0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_VREF_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_EN_OVRD_EN__SHIFT                              0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP__SHIFT                            0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_VREG_SPEEDUP_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN__SHIFT                                    0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_FBCLK_EN_OVRD_EN__SHIFT                            0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL__SHIFT                                         0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_CAL_OVRD_EN__SHIFT                                 0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST__SHIFT                                         0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_RST_OVRD_EN__SHIFT                                 0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT__SHIFT                               0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_ANA_GEARSHIFT_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN__SHIFT                                   0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__MPLLA_OUTPUT_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_0__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN__SHIFT                                 0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN__SHIFT                                 0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_FB_CLK_DIV4_EN_OVRD_EN__SHIFT                      0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN__SHIFT                            0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_DIV5_CLK_EN_OVRD_EN__SHIFT                    0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN__SHIFT                            0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_DIV2_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN__SHIFT                                 0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN__SHIFT                                  0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV_CLK_EN_OVRD_EN__SHIFT                          0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN__SHIFT                              0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_OVRD_OUT_1__MPLLA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_INT_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN__SHIFT                                0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__MPLLA_PMIX_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_FRAC__SHIFT                              0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_PMIX_OVRD_OUT_1__MPLLA_PMIX_INT__SHIFT                               0x6
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_ANA_EN_OVRD_EN__SHIFT                              0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN__SHIFT                                    0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_FBCLK_EN_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL__SHIFT                                         0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST__SHIFT                                         0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_RST_OVRD_EN__SHIFT                                 0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT__SHIFT                                   0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_GEARSHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN__SHIFT                                   0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_OUTPUT_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE__SHIFT                                   0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_CAL_FORCE_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY__SHIFT                                     0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_0__MPLLB_STANDBY_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN__SHIFT                                 0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_L_EN_OVRD_EN__SHIFT                         0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN__SHIFT                                 0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_OUTPUT_R_EN_OVRD_EN__SHIFT                         0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV5_CLK_EN_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN__SHIFT                                0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_DIV2_EN_OVRD_EN__SHIFT                        0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN__SHIFT                                 0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_WORD_CLK_EN_OVRD_EN__SHIFT                         0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_DIV_CLK_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN__SHIFT                             0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__MPLLB_HDMI_DIV_CLK_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_OVRD_OUT_1__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_FRAC_OVRD_EN__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_INT_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN__SHIFT                                0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__MPLLB_PMIX_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                0x4
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_FRAC__SHIFT                              0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_PMIX_OVRD_OUT_1__MPLLB_PMIX_INT__SHIFT                               0x6
//C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_EN__SHIFT                                            0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_COMP_RST__SHIFT                                      0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_MODE__SHIFT                                          0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_VALUE__SHIFT                                         0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RTUNE_OVRD_EN__SHIFT                                       0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_RTUNE_OVRD_OUT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC__SHIFT                                          0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__SUP_ANA_MISC_OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_OVRD_OUT__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE__SHIFT                            0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_COARSE_TUNE_OVRD_EN__SHIFT                    0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE__SHIFT                              0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__MPLLA_FINE_TUNE_OVRD_EN__SHIFT                      0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_TUNE_OVRD_OUT_0__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_MEAS_VREG__SHIFT                                   0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_1_1__SHIFT                                        0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SELECT__SHIFT                                  0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_OVRD_FAST_START__SHIFT                             0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_FAST_START_REG__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_VREG_BOOST__SHIFT                                  0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_7_7__SHIFT                                        0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_BYPASS_BG__SHIFT                                   0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_RX_VCO_VREF_2__SHIFT                           0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_ATB_SWITCH_7__SHIFT                                0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__RESERVED_12_11__SHIFT                                      0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_CHOP_EN_INT__SHIFT                                 0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG00__SUP_ANA_SEL_VBG_VREF_TX__SHIFT                             0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_REF_HYST__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_VBG_VREF_RX__SHIFT                             0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_SEL_RX_VCO_VREF_1_0__SHIFT                         0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__RESERVED_7_6__SHIFT                                        0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_0__SHIFT                                0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_1__SHIFT                                0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_2__SHIFT                                0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_3__SHIFT                                0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_4__SHIFT                                0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_5__SHIFT                                0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_ATB_SWITCH_6__SHIFT                                0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG01__SUP_ANA_TEMP_MEAS__SHIFT                                   0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBF__SHIFT                                 0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_SEL_ATBP__SHIFT                                 0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_ATB__SHIFT                                      0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_CHOP__SHIFT                                 0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_DAC_MODE__SHIFT                                 0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_TX_RBOOST_EN__SHIFT                             0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_6_6__SHIFT                                        0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__SUP_ANA_RT_EN_FRCON__SHIFT                                 0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_11_8__SHIFT                                       0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG02__RESERVED_15_12__SHIFT                                      0xc
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_1_0__SHIFT                                        0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_3_2__SHIFT                                        0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_5_4__SHIFT                                        0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_7_6__SHIFT                                        0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__SUP_ANA_REF_OVERRIDE_RING_CNTRL__SHIFT                     0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_14_9__SHIFT                                       0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG03__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__RESERVED_6_0__SHIFT                                    0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__SEL_VPLL_REF__SHIFT                                    0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__DCO_FINETUNE_CREG_OVR__SHIFT                           0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_SUP_ANA_CREG0_OVRD__VREG_FB_DIV_CTRL__SHIFT                                0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_0_0__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_PR_BYPASS__SHIFT                          0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_MODE_OLD_SSC__SHIFT                            0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PR_BYPASS__SHIFT                               0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__RESERVED_4_4__SHIFT                                      0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_LPN_VREG__SHIFT                                0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_PFD_PW_CTRL__SHIFT                             0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_ENABLE__SHIFT                             0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_ENABLE_REG__SHIFT                              0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_CAL__SHIFT                                0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_CAL_REG__SHIFT                                 0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_FB_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_FB_CLK_EN_REG__SHIFT                           0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_OVRD_RESET__SHIFT                              0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG00__MPLLA_ANA_RESET_REG__SHIFT                               0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_0__SHIFT                               0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_1__SHIFT                               0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_2__SHIFT                               0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_3__SHIFT                               0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_4__SHIFT                               0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_5__SHIFT                               0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_6__SHIFT                               0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_7__SHIFT                               0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_8__SHIFT                               0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_9__SHIFT                               0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_10__SHIFT                              0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_11__SHIFT                              0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_12__SHIFT                              0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_13__SHIFT                              0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_14__SHIFT                              0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG01__MPLLA_ANA_MEAS_IV_15__SHIFT                              0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_16__SHIFT                              0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_17__SHIFT                              0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_18__SHIFT                              0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_19__SHIFT                              0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_20__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_21__SHIFT                              0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_ATB_SELECT__SHIFT                              0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_22__SHIFT                              0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_23__SHIFT                              0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_24__SHIFT                              0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_25__SHIFT                              0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_26__SHIFT                              0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_27__SHIFT                              0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__MPLLA_ANA_MEAS_IV_28__SHIFT                              0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG02__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GEAR_SHIFT_EN__SHIFT                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GEAR_SHIFT_EN__SHIFT                           0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_OVRD_GS_BW__SHIFT                              0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_GS_BW__SHIFT                                   0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__RESERVED_12_12__SHIFT                                    0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_VREG_OVERRIDE_RING_CNTRL__SHIFT                    0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_PMIX_DLL_BYOAZ__SHIFT                              0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG03__MPLLA_ANA_PMIX_MODE_90__SHIFT                            0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__RESERVED_2_0__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_DSQ_EN__SHIFT                                      0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_PFD__SHIFT                              0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_S__SHIFT                                0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_CP__SHIFT                               0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_PMIX__SHIFT                             0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_RIGHT__SHIFT                            0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG04__MPLLA_VREG_BOOST_LEFT__SHIFT                             0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_CLK_BYPASS__SHIFT                                   0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_RIGHT_BYPASS__SHIFT                                 0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_LEFT_BYPASS__SHIFT                                  0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_CP_BYPASS__SHIFT                                    0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__VREG_PFD_BYPASS__SHIFT                                   0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG05__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_7_0__SHIFT                                  0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLA_ANA_CREG0_OVRD__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEAR_RC_FILT__SHIFT                       0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_TEST_RC_FILT__SHIFT                       0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_VREG_DIV__SHIFT                           0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_VBG_EN__SHIFT                                  0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_COUNT_SEL_LOCK__SHIFT                          0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__RESERVED_7_6__SHIFT                                      0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_PR_BYPASS__SHIFT                          0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_PR_BYPASS__SHIFT                               0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_OVRD_GEARSHIFT__SHIFT                          0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_GEARSHIFT_REG__SHIFT                           0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_TEST_LOCK_GEAR__SHIFT                          0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_EN_CAL_SPO__SHIFT                              0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTR_LVLCONV__SHIFT                             0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG00__MPLLB_ANA_CTRL_MODE_90__SHIFT                            0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_ENABLE__SHIFT                             0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ENABLE_REG__SHIFT                              0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_CAL__SHIFT                                0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_CAL_REG__SHIFT                                 0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_FB_CLK_EN__SHIFT                          0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_FB_CLK_EN_REG__SHIFT                           0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_OVRD_RESET__SHIFT                              0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_RESET_REG__SHIFT                               0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_MEAS_IV_WRAP__SHIFT                            0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__RESERVED_14_13__SHIFT                                    0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG01__MPLLB_ANA_ATB_SELECT__SHIFT                              0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_INTCLK_DOUBLER__SHIFT                 0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_OSC_FREQ__SHIFT                       0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RING_OVERRIDE__SHIFT                  0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_PLL_RESERVED__SHIFT                       0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREF_VMARG__SHIFT                          0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_OVERFLOW__SHIFT                           0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_MPLL_RESERVED__SHIFT                      0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLK_BYP__SHIFT                        0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_CLKPMIX_BYP__SHIFT                    0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_RIGHT_BYP__SHIFT                      0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTR_VREG_LEFT_BYP__SHIFT                       0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG02__MPLLB_ANA_CTRL_DIV4_MODE__SHIFT                          0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_MPLL_DIV16P5_CLK_EN__SHIFT                 0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK_EN__SHIFT                         0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_TEST_CLK__SHIFT                            0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_STANDBY_MODE__SHIFT                        0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_LEG_SR_CON__SHIFT                          0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_SPO_SPEED_OVERRIDE__SHIFT                      0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__RESERVED_11_8__SHIFT                                     0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_CASC_FAST_START__SHIFT                     0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_V2I_OVERRIDE__SHIFT                        0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG03__MPLLB_ANA_CTR_PFD_RST__SHIFT                             0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_ICP_INT__SHIFT                             0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_SENSE_SW__SHIFT                         0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_OVERRIDE_BIASREF__SHIFT                    0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_IBIAS__SHIFT                               0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_DIV_SPO__SHIFT                            0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CP_INT_IN__SHIFT                           0x5
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_VREG_CP__SHIFT                             0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_V2I_STUO__SHIFT                            0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_REGS_PLL_DDR__SHIFT                        0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTRL_PLL_RING__SHIFT                           0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_CALIB_CURR__SHIFT                          0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_OUT_VREG_REF__SHIFT                    0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_VREG_INT_CLK__SHIFT                    0xd
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG04__MPLLB_ANA_CTR_PLL_V2I_VREG__SHIFT                        0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PLL_VREG_FILT__SHIFT                       0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_PL_RING__SHIFT                        0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_VREG_IN_CURR__SHIFT                        0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_GAIN_3_2__SHIFT                    0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_RESAMP__SHIFT                      0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_PLL_SPEED__SHIFT                       0x7
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_SPO_BYPASS_EN__SHIFT                       0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_CP_8X__SHIFT                               0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_PFD__SHIFT                                 0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_EN_COUNT__SHIFT                            0xb
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_TEST_CASC__SHIFT                           0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG05__MPLLB_ANA_CTR_RC_FITER__SHIFT                            0xd
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_INT_REF__SHIFT                          0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CP_PROP_REF__SHIFT                         0x3
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_MODE_H_PLL__SHIFT                          0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DOUBLER_GAIN__SHIFT                        0x9
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_SPOLATCH_PH__SHIFT                         0xa
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_VREF_VMARG__SHIFT                          0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DLL__SHIFT                                 0xe
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG06__MPLLB_ANA_CTR_DSQ__SHIFT                                 0xf
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__RESERVED_0_0__SHIFT                                      0x0
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_RST_ALIG__SHIFT                            0x1
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_PLL_DAC__SHIFT                             0x2
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_REGS_CP_PLL__SHIFT                         0x4
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_SPO_PLL_STEP__SHIFT                        0x6
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_PHASE_SEL_LOCK__SHIFT                          0x8
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_CTR_VREG_LR_CLK_GAIN__SHIFT                    0xc
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG07__MPLLB_ANA_TEST_BOOST__SHIFT                              0xe
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                 0x0
//C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD
#define C20_PHY_CR1_SUP_DIG_ANA_XF_MPLLB_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                 0x0
//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__PHY_FUNC_RST__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL__RESERVED_15_1__SHIFT                                                  0x1
//C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__CREG_CLK_CG_EN_OVRD__SHIFT                                   0x0
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CLK_GATE_CTL__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN__SHIFT                                                 0x2
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLA_SSC_EN_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE__SHIFT                                       0x4
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_INIT_CAL_DISABLE_OVRD_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN__SHIFT                                                 0x6
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__MPLLB_SSC_EN_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE__SHIFT                                              0x8
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__HDMIMODE_ENABLE_OVRD_EN__SHIFT                                      0x9
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ__SHIFT                                                    0xa
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_OVRD_EN__SHIFT                                            0xb
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RTUNE_REQ_SEQ_MODE__SHIFT                                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_CMN_CTL_1__RESERVED_15_13__SHIFT                                               0xd
//C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_OFF_TIME__SHIFT                                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__MPLL_FORCE_ON_TIME__SHIFT                                         0x6
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CONFIG__RESERVED_15_10__SHIFT                                             0xa
//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__ATE_ALU_OPCODE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_CTRL__RESERVED_15_4__SHIFT                                             0x4
//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ADDR__ADDR__SHIFT                                                      0x0
//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_DATA__DATA__SHIFT                                                      0x0
//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__ATE_ALU_ACCUM_SIGN__SHIFT                                       0x0
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_FLAGS__RESERVED_15_1__SHIFT                                            0x1
//C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM
#define C20_PHY_CR1_RAWCMN_DIG_ATE_ALU_ACCUM__VAL__SHIFT                                                      0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLL_IN
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_INIT_CAL_DISABLE__SHIFT                                         0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLA_SSC_EN__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_INIT_CAL_DISABLE__SHIFT                                         0x2
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__MPLLB_SSC_EN__SHIFT                                                   0x3
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_IN__RESERVED_15_4__SHIFT                                                  0x4
//C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE
#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__DONE__SHIFT                                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                            0x1
//C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS
#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__EXT_DONE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWCMN_DIG_STATIC_CONFIG_STATUS__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS
#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__INT_CFG_DONE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__CMN_CAL_DONE__SHIFT                                          0x1
#define C20_PHY_CR1_RAWCMN_DIG_FW_CONFIG_STATUS__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1
#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__EXT_RTUNE_DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__VGEN_CAL_DONE__SHIFT                                             0x1
#define C20_PHY_CR1_RAWCMN_DIG_CMN_STATUS_1__RESERVED_15_2__SHIFT                                             0x2
//C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLA_CLK_OVRD__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__MPLLB_CLK_OVRD__SHIFT                                     0x1
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_CLK_ASYNC_OVRD__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x2
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0x3
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0x4
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0x5
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLA_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_VAL__SHIFT                     0x7
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_BANK_SEL_OVRD_EN__SHIFT                      0x9
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT                     0xa
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_FORCE_EN_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT                      0xc
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__MPLLB_RECAL_SKIP_EN_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_RAWCMN_DIG_MPLL_RECAL_BANK_OVRD__RESERVED_15_14__SHIFT                                    0xe
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__MPLLA_FRAC_ATOMIC_MODE__SHIFT                               0x1
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_CFG_UPDATE_EN__SHIFT                             0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__MPLLB_FRAC_ATOMIC_MODE__SHIFT                               0x1
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_FRAC_UPDATE__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION
#define C20_PHY_CR1_RAWCMN_DIG_CONFIG_MASTER_VERSION__CONFIG_VERSION__SHIFT                                   0x0
//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VAL__SHIFT                                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__VALID__SHIFT                                                  0x8
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_0__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VAL__SHIFT                                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__VALID__SHIFT                                                  0x8
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_1__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VAL__SHIFT                                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__VALID__SHIFT                                                  0x8
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_2__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VAL__SHIFT                                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__VALID__SHIFT                                                  0x8
#define C20_PHY_CR1_RAWCMN_DIG_CTLE_OFST_CFG_3__RESERVED_15_9__SHIFT                                          0x9
//C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL
#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_ROM_ACCESS_SEL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__CREG_RAM_ACCESS_SEL__SHIFT                                    0x1
#define C20_PHY_CR1_RAWCMN_DIG_CREG_ACCESS_CTL__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__CNTX_RSTR_HP_EN__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_RSTR_REQ_CTRL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__CMN_CNTX_SEL_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_0__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__MPLLA_CNTX_SEL_OVRD_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_1__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__MPLLB_CNTX_SEL_OVRD_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWCMN_DIG_CNTX_SEL_OVRD_IN_2__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_0
#define C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_0__VAL__SHIFT                                                        0x0
//C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_1
#define C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_1__VAL__SHIFT                                                        0x0
//C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_2
#define C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_2__VAL__SHIFT                                                        0x0
//C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_3
#define C20_PHY_CR1_RAWCMN_DIG_CMN_DEBUG_3__VAL__SHIFT                                                        0x0
//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__SUP_MISC__SHIFT                                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__TX_VBOOST_LVL__SHIFT                                           0x8
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_0__RESERVED_15_11__SHIFT                                          0xb
//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RX_VREF_CTRL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__TXDN_TERM_OFFSET__SHIFT                                        0x5
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_1__RESERVED_15_14__SHIFT                                          0xe
//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RX_TERM_OFFSET__SHIFT                                          0x0
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__TXUP_TERM_OFFSET__SHIFT                                        0x5
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_2__RESERVED_15_14__SHIFT                                          0xe
//C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__UNIQUE_ID__SHIFT                                               0x0
#define C20_PHY_CR1_RAWCMN_DIG_SUP_CNTX_CFG_3__RESERVED_15_10__SHIFT                                          0xa
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__FB_CLK_DIV4_EN__SHIFT                                        0xd
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_0__SHORT_LOCK_EN__SHIFT                                         0xf
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__TX_CLK_DIV__SHIFT                                            0x8
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0xb
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__CTL_BUF_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_1__BW_THRESHOLD__SHIFT                                          0xe
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_2__BW_LOW__SHIFT                                                0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_3__BW_HIGH__SHIFT                                               0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__REF_CLK_MPLLA_DIV__SHIFT                                     0xa
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__LC_FREQSEL__SHIFT                                            0xd
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xe
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_6__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9
#define C20_PHY_CR1_RAWCMN_DIG_MPLLA_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__MULTIPLIER__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__DIV_CLK_EN__SHIFT                                            0xc
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_0__TX_CLK_DIV__SHIFT                                            0xd
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__DIV_MULTIPLIER__SHIFT                                        0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__WORD_CLK_DIV__SHIFT                                          0x8
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__CAL_DAC_CODE__SHIFT                                          0xa
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_INT__SHIFT                                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__CP_PROP__SHIFT                                               0x7
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_2__FREQ_VCO__SHIFT                                              0xe
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_INT_GS__SHIFT                                             0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__CP_PROP_GS__SHIFT                                            0x7
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_3__V2I__SHIFT                                                   0xe
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_4__SSC_PEAK_LSB__SHIFT                                          0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_5__SSC_STEP_SIZE_LSB__SHIFT                                     0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_PEAK_MSB__SHIFT                                          0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_STEP_SIZE_MSB__SHIFT                                     0x4
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__SSC_UP_SPREAD__SHIFT                                         0x9
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__REF_CLK_MPLLB_DIV__SHIFT                                     0xa
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__FRAC_EN__SHIFT                                               0xd
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_6__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_7__FRAC_DEN__SHIFT                                              0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_8__FRAC_QUOT__SHIFT                                             0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_9__FRAC_REM__SHIFT                                              0x0
//C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_DIV__SHIFT                                             0x0
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__HDMI_PIXEL_CLK_DIV__SHIFT                                   0x3
#define C20_PHY_CR1_RAWCMN_DIG_MPLLB_CNTX_CFG_10__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_PGATE_BL_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__SRAM_AON_BL_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__FW_STOP_EN__SHIFT                                        0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_PGATE_BL_EN__RESERVED_15_3__SHIFT                                     0x3
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__MPLLA_TUNE_BYP__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_BANK_0__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__MPLLA_TUNE_DONE_BANK_0__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_BANK_1__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__MPLLA_TUNE_DONE_BANK_1__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_BANK_2__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__MPLLA_TUNE_DONE_BANK_2__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_BANK_3__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__MPLLA_TUNE_DONE_BANK_3__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__MPLLA_CAL_BANK_SEL__SHIFT                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__MPLLA_TUNE_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__MPLLB_TUNE_BYP__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_CTRL__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_BANK_0__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__MPLLB_TUNE_DONE_BANK_0__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_BANK_1__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__MPLLB_TUNE_DONE_BANK_1__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_BANK_2__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__MPLLB_TUNE_DONE_BANK_2__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_BANK_3__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__MPLLB_TUNE_DONE_BANK_3__SHIFT                           0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_BANK_3__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__MPLLB_CAL_BANK_SEL__SHIFT                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__MPLLB_TUNE_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE_DONE__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__MPLLA_TUNE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_TUNE__RESERVED_15_12__SHIFT                                          0xc
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__MPLLB_TUNE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_TUNE__RESERVED_15_12__SHIFT                                          0xc
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__MPLLA_IN_RECAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLA_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__MPLLB_IN_RECAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLLB_IN_RECAL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PMA_PWR_STABLE_OVRD__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PCS_PWR_STABLE_OVRD__SHIFT                                     0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_VAL__SHIFT                                       0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_RESET_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_VAL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__PG_MODE_EN_OVRD_EN__SHIFT                                      0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_IN__RESERVED_15_6__SHIFT                                           0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PMA_PWR_EN_OVRD__SHIFT                                        0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__PCS_PWR_EN_OVRD__SHIFT                                        0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_CPM_ENTRY_ISO__SHIFT                                       0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__EN_STATIC_PG_MODE_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_VAL__SHIFT                              0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__ANA_ISOLATION_EN_OVRD_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_PG_OVRD_OUT__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_VAL__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLA_FORCE_EN_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__MPLLB_FORCE_EN_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_VAL__SHIFT                                    0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT                                     0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_REPEAT_CLK_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_VAL__SHIFT                            0x8
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__REF_ALT_CLK_LP_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__FW_CLK_ACK_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_IN__RESERVED_15_12__SHIFT                                         0xc
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLA_FORCE_EN__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__MPLLB_FORCE_EN__SHIFT                                            0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_CLK_EN__SHIFT                                                0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_REPEAT_CLK_EN__SHIFT                                         0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__REF_ALT_CLK_LP_SEL__SHIFT                                        0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__FW_CLK_ACK__SHIFT                                                0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_IN_0__RESERVED_15_6__SHIFT                                             0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_VAL__SHIFT                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLA_FORCE_ACK_OVRD_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_VAL__SHIFT                              0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__MPLLB_FORCE_ACK_OVRD_EN__SHIFT                               0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_VAL__SHIFT                                  0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__REF_CLK_REQ_OVRD_EN__SHIFT                                   0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_VAL__SHIFT                                   0x6
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__FW_CLK_REQ_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OVRD_OUT__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLA_FORCE_ACK__SHIFT                                          0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__MPLLB_FORCE_ACK__SHIFT                                          0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__REF_CLK_REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__FW_CLK_REQ__SHIFT                                               0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_OUT_0__RESERVED_15_4__SHIFT                                            0x4
//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL
#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__PMA_MPLLA_RECAL_BANK_SEL__SHIFT                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLA_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL
#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__PMA_MPLLB_RECAL_BANK_SEL__SHIFT                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_PMA_MPLLB_RECAL_BANK_SEL__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS
#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_INIT__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__CMNCAL_MPLL_DONE__SHIFT                                0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_MPLL_STATUS__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS
#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_INIT__SHIFT                              0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__CMNCAL_RTUNE_DONE__SHIFT                              0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_CMNCAL_RTUNE_STATUS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RTUNE_RX_VAL_0__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_0__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RTUNE_TXDN_VAL_0__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_0__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RTUNE_TXAVG_VAL_0__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_0__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RTUNE_RX_VAL_1__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_1__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RTUNE_TXDN_VAL_1__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_1__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RTUNE_TXAVG_VAL_1__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_1__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RTUNE_RX_VAL_2__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_2__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RTUNE_TXDN_VAL_2__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RTUNE_TXAVG_VAL_2__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_2__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RTUNE_RX_VAL_3__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_3__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RTUNE_TXDN_VAL_3__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_3__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RTUNE_TXAVG_VAL_3__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_3__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RTUNE_RX_VAL_4__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_4__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RTUNE_TXDN_VAL_4__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_4__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RTUNE_TXAVG_VAL_4__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_4__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RTUNE_RX_VAL_5__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_5__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RTUNE_TXDN_VAL_5__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_5__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RTUNE_TXAVG_VAL_5__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_5__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RTUNE_RX_VAL_6__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_6__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RTUNE_TXDN_VAL_6__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_6__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RTUNE_TXAVG_VAL_6__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_6__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RTUNE_RX_VAL_7__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_RX_VAL_7__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RTUNE_TXDN_VAL_7__SHIFT                                  0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXDN_VAL_7__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RTUNE_TXAVG_VAL_7__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_TXAVG_VAL_7__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_VAL__SHIFT                             0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_EXT_LD_DONE_OVRD_EN__SHIFT                              0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_VAL__SHIFT                             0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BYPASS_MODE_OVRD_EN__SHIFT                              0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_VAL__SHIFT                         0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__SRAM_BOOTLOAD_BYPASS_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OVRD_IN__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BYPASS_MODE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_EXT_LD_DONE__SHIFT                                           0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__SRAM_BOOTLOAD_BYPASS__SHIFT                                       0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_IN__RESERVED_15_5__SHIFT                                              0x5
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__SRAM_INIT_DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_OUT__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_FW_VERSION_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION
#define C20_PHY_CR1_RAWCMN_DIG_AON_RAW_VERSION__VAL__SHIFT                                                    0x0
//C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_INIT__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_CAL_DONE__SHIFT                                      0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RTUNE_IN_RECAL__SHIFT                                      0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_RTUNE_IN_RECAL__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_EOF_ADDR__SRAM_EOF_ADDR__SHIFT                                        0x0
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_BOC_ADDR__SRAM_BOC_ADDR__SHIFT                                        0x0
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_CLK_SEL_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_VAL__SHIFT                                  0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__CR_INT_CLK_SEL_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_VAL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__FW_STOP_REQ_OVRD_EN__SHIFT                                      0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_VAL__SHIFT                                     0x6
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__SRAM_CLK_EN_OVRD_EN__SHIFT                                      0x7
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_VAL__SHIFT                                      0x8
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__ROM_CLK_EN_OVRD_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_0__RESERVED_15_10__SHIFT                                           0xa
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_CTL_1__FW_STOP_ACK_OVRD_EN__SHIFT                                      0x8
//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB_TIMEOUT_MASK__SHIFT                                     0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__DIS_APB0_DMA_ARBT_LOCK__SHIFT                                   0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1
#define C20_PHY_CR1_RAWCMN_DIG_AON_APB_CFG_1__APB_TIMEOUT_VAL__SHIFT                                          0x0
//C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_REF_CLK_ACK__SHIFT                                       0x1
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__ISOLATE_EN__SHIFT                                            0x2
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_EN__SHIFT                                            0x3
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_EN__SHIFT                                            0x4
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PMA_PWR_STABLE__SHIFT                                        0x5
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__PCS_PWR_STABLE__SHIFT                                        0x6
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__TX_FW_CLK_REQ__SHIFT                                         0x7
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RX_FW_CLK_REQ__SHIFT                                         0x8
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_SEL__SHIFT                                            0x9
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_EXT__SHIFT                                         0xa
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_INT__SHIFT                                         0xb
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_INT_CLK_SEL__SHIFT                                        0xc
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_REF__SHIFT                                         0xd
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__CR_CLK_EN_FW__SHIFT                                          0xe
#define C20_PHY_CR1_RAWCMN_DIG_AON_SUP_STATUS_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__MPLL_CNTX_RSTR_CTRL__SHIFT                            0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_MPLL_CNTX_RSTR_CTRL__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION
#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__METADATA_LOCATION__SHIFT                                0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_METADATA_LOCATION__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST__SHIFT                         0x0
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR_OFST_OVRD__SRAM_REC_ADDR_OFST_OVRD_EN__SHIFT                 0xf
//C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR
#define C20_PHY_CR1_RAWCMN_DIG_AON_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                        0x0
//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE0_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE0_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR1_LANE0_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR1_LANE0_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL
#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE0_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE0_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR1_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL
#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR
#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR1_LANE0_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR1_LANE0_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR1_LANE0_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE0_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE1_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE1_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR1_LANE1_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR1_LANE1_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL
#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE1_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE1_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR1_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL
#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR
#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR1_LANE1_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR1_LANE1_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR1_LANE1_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE1_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE2_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE2_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR1_LANE2_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR1_LANE2_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL
#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE2_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE2_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR1_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL
#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR
#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR1_LANE2_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR1_LANE2_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR1_LANE2_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE2_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE3_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE3_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR1_LANE3_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR1_LANE3_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL
#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR1_LANE3_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANE3_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR1_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL
#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR
#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR1_LANE3_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR1_LANE3_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR1_LANE3_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANE3_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE0_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE0_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE1_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE1_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE2_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE2_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANE3_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANE3_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR1_RAWLANEAON0_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR1_RAWLANEAON1_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR1_RAWLANEAON2_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR1_RAWLANEAON3_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__EN__SHIFT                                                    0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE__SHIFT                                        0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_OVRD_IN__RESERVED_15_6__SHIFT                                         0x6
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__CLK_RDY_OVRD_EN__SHIFT                                       0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_VAL__SHIFT                                        0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_VAL__SHIFT                                       0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_VAL__SHIFT                                      0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_VAL__SHIFT                                          0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_VAL__SHIFT                                          0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_VAL__SHIFT                                       0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_VAL__SHIFT                                        0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_VAL__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__ALIGN_WIDE_XFER_EN_OVRD_EN__SHIFT                            0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_VAL__SHIFT                                    0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_VAL__SHIFT                                0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__DETECT_RX_REQ_OVRD_EN__SHIFT                                 0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_1__FLYOVER_EN_OVRD_EN__SHIFT                                    0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__NYQUIST_DATA__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__EN__SHIFT                                                    0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_2__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_POST_CURSOR__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_MAIN_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__TX_EQ_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_3__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC__SHIFT                                     0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__TX_BYPASS_EQ_CALC_OVRD_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_4__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_ASYNC_FIFO_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE2LANE_DSKW_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_LANE_DSKW_EN_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR__SHIFT                                          0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DRV_EN_KR_OVRD_EN__SHIFT                                  0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN__SHIFT                                        0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_CLK_DSKW_EN_OVRD_EN__SHIFT                                0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS__SHIFT                                     0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_VREG_TX_BYPASS_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_IN_5__TX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_TX_ACK__SHIFT                                              0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__DETRX_RESULT__SHIFT                                           0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__EN_DETRX_RESULT__SHIFT                                        0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS__SHIFT                                              0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__CALIB_STS_OVRD_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_OUT__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_TX2RX_SER_LB__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_RX2TX_PAR_LB__SHIFT                                     0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__LANE_XCVR_MODE__SHIFT                                        0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_LANE_ASIC_IN__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__CLK_RDY__SHIFT                                               0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RESET__SHIFT                                                 0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__REQ__SHIFT                                                   0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__LPD__SHIFT                                                   0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__PSTATE__SHIFT                                                0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__WIDTH__SHIFT                                                 0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__ALIGN_WIDE_XFER_EN__SHIFT                                    0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_0__MPLLB_SEL__SHIFT                                             0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DETECT_RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__BEACON_EN__SHIFT                                             0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__IBOOST_LVL__SHIFT                                            0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__VBOOST_EN__SHIFT                                             0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__TX_MAIN_CURSOR__SHIFT                                        0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_PRE_CURSOR__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__TX_POST_CURSOR__SHIFT                                        0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_2__RESERVED_15_14__SHIFT                                        0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__TX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_IN_3__RESERVED_15_4__SHIFT                                         0x4
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__TX_ACK__SHIFT                                                 0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__DETRX_RESULT__SHIFT                                           0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__CALIB_STS__SHIFT                                              0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_ASIC_OUT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__TX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_TX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__TX_P0_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_REFGEN_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VCM_HOLD__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_CLK_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_RESET__SHIFT                                0x3
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_SERIAL_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DIG_CLK_EN__SHIFT                               0x5
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_DATA_EN__SHIFT                                  0x6
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_RXDET__SHIFT                              0x7
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ALLOW_VBOOST__SHIFT                             0x8
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_DCC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_TX_BLEEDER_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                 0xb
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__TX_P0S_ANA_WORD_CLK_EN__SHIFT                          0xc
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__TX_P1_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_REFGEN_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VCM_HOLD__SHIFT                               0x1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_RESET__SHIFT                                  0x3
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_SERIAL_EN__SHIFT                              0x4
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DIG_CLK_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_DATA_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_RXDET__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ALLOW_VBOOST__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_DCC_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_TX_BLEEDER_EN__SHIFT                     0xa
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                   0xb
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__TX_P2_ANA_WORD_CLK_EN__SHIFT                            0xc
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_REFGEN_EN_TIME__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_REFGEN_EN_TIME__SHIFT                        0x7
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__TX_CLK_EN_TIME__SHIFT                                0x8
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0__FAST_TX_CLK_EN_TIME__SHIFT                           0xf
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__TX_VCM_HOLD_TIME__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1__SKIP_TX_VCM_HOLD_WAIT__SHIFT                         0xf
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_VBOOST_DIS_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__TX_RESET_TIME__SHIFT                                 0xd
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_RXDET_TIME__SHIFT                                 0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__FAST_TX_RXDET__SHIFT                                 0xa
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3__TX_VREG_FAST_START_TIME__SHIFT                       0xb
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_VCM_HOLD_GS_TIME__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__TX_SERIAL_EN_TIME__SHIFT                             0xb
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_4__FAST_TX_SERIAL_EN_TIME__SHIFT                        0xf
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__TX_BLEEDER_EN_TIME__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_5__RESERVED_15_4__SHIFT                                 0x4
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_RATE_CHG_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__SKIP_CLK_ALIGN_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__DTB_SEL__SHIFT                                                0x3
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x6
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_DCC_DAC_WRITE_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_REQ_DISABLE__SHIFT                                         0x8
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CLK_LB_LATE_EN__SHIFT                                      0x9
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__TX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0xa
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_CTL__RESERVED_15_11__SHIFT                                         0xb
//C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__TX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANEX_DIG_TX_PWRCTL_TX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__VAL__SHIFT                                    0x0
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                          0x9
//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__OVRD_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_TX_DCC_CM_IDAC_OFST__RESERVED_15_9__SHIFT                            0x9
//C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__TX_DCC_DAC_FSM_STATE__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_TX_DCC_CTL_STAT__RESERVED_15_5__SHIFT                                           0x5
//C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_PAUSE__SHIFT                                              0x1
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED__SHIFT                                              0x2
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0x3
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__SC_DWORD_COUNT_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CTL0__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANEX_DIG_TX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__STARTUP_DELAY__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_32B16B8B_MODE__SHIFT                   0xa
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_0__TX_NUM_2UI_SHIFTS_40B20B10B_MODE__SHIFT                  0xd
//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RETRIG_CLK_ALIGN__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__STICKY_LATE_FILTER_DIS__SHIFT                            0x1
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_TX_CTL_1__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__SHIFT_CNT__SHIFT                                 0x0
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__FSM_STATE__SHIFT                                 0x7
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__TX_CLK_STATE__SHIFT                              0xa
#define C20_PHY_CR1_LANEX_DIG_TX_CLK_ALIGN_CLK_ALIGN_STATUS__RESERVED_15_11__SHIFT                            0xb
//C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__TRIGGER_ERR__SHIFT                                                0x4
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__PAT0__SHIFT                                                       0x5
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_CTL__RESERVED_15_15__SHIFT                                             0xf
//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_0__PAT1_15_0__SHIFT                                               0x0
//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_1__PAT1_31_16__SHIFT                                              0x0
//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_2__PAT1_47_32__SHIFT                                              0x0
//C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3
#define C20_PHY_CR1_LANEX_DIG_TX_LBERT_PAT1_3__EXT_PAT_47_32__SHIFT                                           0x0
//C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT
#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__TX_CAL_CODE_BIN__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_TX_LVL_CALC_STAT__RESERVED_15_4__SHIFT                                          0x4
//C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL
#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_RD_PTR_START__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__TX_FIFO_BYPASS__SHIFT                                              0x2
#define C20_PHY_CR1_LANEX_DIG_TX_FIFO_CTL__RESERVED_15_3__SHIFT                                               0x3
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLA_CLK_EN_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_MPLLB_CLK_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_EN_OVRD_EN__SHIFT                              0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DIV4_EN_OVRD_EN__SHIFT                             0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_CLK_SHIFT_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET__SHIFT                                       0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_RESET_OVRD_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_SERIAL_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_0__TX_ANA_DATA_EN_OVRD_EN__SHIFT                             0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_REFGEN_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD__SHIFT                                    0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS__SHIFT                                 0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VCM_HOLD_GS_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS__SHIFT                              0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BYPASS_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START__SHIFT                             0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_TX_BLEEDER_EN_OVRD_EN__SHIFT                  0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_VREG_VPTX_BLEEDER_EN_OVRD_EN__SHIFT                0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__TX_ANA_BLEEDER_OVERRIDE__SHIFT                            0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_DATA_RATE_EN_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LB_EN__SHIFT                                   0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_CLK_LBK_EN_OVRD_EN__SHIFT                          0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN__SHIFT                                    0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_RXDET_EN_OVRD_EN__SHIFT                            0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL__SHIFT                                     0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_REF_SEL_OVRD_EN__SHIFT                             0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN__SHIFT                                   0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_VBOOST_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__TX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                         0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_2__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_MISC_EN_OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST__SHIFT                                   0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__TX_ANA_ASYNC_RST_OVRD_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_OVRD_OUT_3__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__TX_ANA_TERM_CODE_OVRD_EN__SHIFT                   0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_OVRD_OUT__RESERVED_15_11__SHIFT                             0xb
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK__SHIFT                        0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__TX_ANA_TERM_CLK_SELF_CLR_DISABLE__SHIFT       0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__VAL__SHIFT                                                0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__OVRD_EN__SHIFT                                            0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_EN__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_DSQ_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_LOOPBACK_TOGGLE_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_LPFBYP_EN__SHIFT                       0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__TX_ANA_DCC_CAL_MUX_SEL__SHIFT                         0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CONFIG__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__TX_ANA_DCC_CAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_OVRD_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_COMP_EN__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__VAL__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__SELF_CLEAR_DISABLE__SHIFT                        0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_CTRL_SEL__RESERVED_15_3__SHIFT                            0x3
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__OVRD_EN__SHIFT                            0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                      0x5
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_DCC_CAL_DATA__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_POST__SHIFT                                    0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK__SHIFT                                0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_OVRD_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_EQ_LFPS_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__TX_ANA_LOAD_CLK_SELF_CLR_DISABLE__SHIFT               0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_0__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__TX_ANA_PRE__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_1__RESERVED_15_7__SHIFT                                  0x7
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                       0x0
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                      0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OVRD_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                        0x0
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLA_CLK_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_MPLLB_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_EN__SHIFT                                      0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DIV4_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_CLK_SHIFT__SHIFT                                   0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_RESET__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_SERIAL_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_DATA_EN__SHIFT                                     0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_REFGEN_EN__SHIFT                                   0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD__SHIFT                                    0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VCM_HOLD_GS__SHIFT                                 0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BYPASS__SHIFT                              0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_FAST_START__SHIFT                             0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_TX_BLEEDER_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_VREG_VPTX_BLEEDER_EN__SHIFT                        0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_0__TX_ANA_LOOPBACK_EN__SHIFT                                 0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_DATA_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_CLK_LB_EN__SHIFT                                   0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_RXDET_EN__SHIFT                                    0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_REF_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_VBOOST_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_FLYOVER_EN__SHIFT                                  0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_ASYNC_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__TX_ANA_WORD_CLK_EN__SHIFT                                 0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_OUT_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_POST__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__TX_ANA_LOAD_CLK__SHIFT                                 0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_0__RESERVED_15_11__SHIFT                                  0xb
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__TX_ANA_PRE__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_1__RESERVED_15_7__SHIFT                                   0x7
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_2__TX_ANA_LEG_PULL_DIR_15_0__SHIFT                        0x0
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_DIR_23_16__SHIFT                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_3__TX_ANA_LEG_PULL_EN_7_0__SHIFT                          0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_EQ_OUT_4__TX_ANA_LEG_PULL_EN_23_8__SHIFT                         0x0
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_CLK_SHIFT_ACK__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETP_RESULT__SHIFT                                0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_RXDETM_RESULT__SHIFT                                0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__TX_ANA_DCC_CAL_RESULT__SHIFT                               0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_STAT_IN_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_CLK_SHIFT__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_SHIFT_REG__SHIFT                               0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DC_MODE_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__RBOOST_TEST_EN__SHIFT                                     0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_VCM_HOLD__SHIFT                               0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_VCM_HOLD_REG__SHIFT                                0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_TX_LOOPBACK__SHIFT                            0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_LOOPBACK_EN_REG__SHIFT                             0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_REFGEN_EN_REG__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_DIV_EN_REG__SHIFT                              0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_DATA_EN_REG_INT__SHIFT                             0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_SERIAL_EN_REG__SHIFT                               0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_EN__SHIFT                                     0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_CLK_LB_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG00__TX_ANA_OVRD_LB_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_DRV_SOURCE_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVRD_ALT_BUS__SHIFT                                0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPH__SHIFT                                     0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VPTX__SHIFT                                    0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_LVT__SHIFT                                  0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_DIV4_EN__SHIFT                                 0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_JTAG_DATA_REG__SHIFT                               0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OSC_VP_CELL__SHIFT                                 0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_GD__SHIFT                                      0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_MEAS_ATB_DCC_CAL_MUX__SHIFT                        0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_DCC_COMP__SHIFT                                0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VPTX__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_OVERRIDE_REGREF__SHIFT                             0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_IBOOST__SHIFT                                  0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG01__TX_ANA_ATB_VDD__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VCM__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSM__SHIFT                                    0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXSP__SHIFT                                    0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFM__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_TXFP__SHIFT                                    0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_RXDETREF__SHIFT                                0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_NBIAS__SHIFT                                   0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_PBIAS__SHIFT                                   0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_MEAS_ATB_VPH_HALF__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_S_ENABLE__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVERRIDE_VREF_BOOST_REF__SHIFT                     0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST_VREF__SHIFT                             0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_ATB_VBOOST__SHIFT                                  0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_BOOST_VPTX_MODE_N__SHIFT                           0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_VBOOST_EN_REG__SHIFT                               0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG02__TX_ANA_OVRD_VBOOST_EN__SHIFT                              0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_OVRD__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_TERM_CODE_REG_9_2__SHIFT                           0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_CM__SHIFT                         0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_DCC_CAL_VDAC_DIFF__SHIFT                       0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_VPTX__SHIFT                               0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_OVERRIDE_REGREF_VPTX__SHIFT                        0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_PULL_DN_REG__SHIFT                                 0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_RES_PULLDN_EN_N__SHIFT                             0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG03__TX_ANA_ATB_VREG_TX__SHIFT                                 0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_SEL_VP_MUX_CELL__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_MUX_CELL__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_TX_BOOST__SHIFT                               0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_PMOS__SHIFT                                    0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_NMOS__SHIFT                                    0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MEAS_ATB_BIAS_VPTX__SHIFT                          0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVERRIDE_RXDETREF__SHIFT                           0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OSC_VP_ULVT__SHIFT                                 0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_DSQ_ACFB_ENB__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_LFPS_HIGH_PRIORITY__SHIFT                          0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLB_CLK_EN_REG__SHIFT                            0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_MPLLA_CLK_EN_REG__SHIFT                            0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_OVRD_MPLLAB_EN__SHIFT                              0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG04__TX_ANA_VREG_RING_CTRL__SHIFT                              0xe
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_PULL_UP_REG__SHIFT                                 0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_MODE__SHIFT                                0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_OVRD__SHIFT                            0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_IBOOST_CODE_REG__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_CMP_TRIM__SHIFT                            0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OVERRIDE_RING_CTRL__SHIFT                          0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_BIAS_CURR_MODE__SHIFT                              0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_OSC_VREG_CP__SHIFT                                 0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_VPTX_BYPASS__SHIFT                            0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG05__TX_ANA_VREG_CP_GAIN_CTRL__SHIFT                           0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__RESERVED_14_0__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG0_OVRD__TX_ANA_SLEW_RATE_EN__SHIFT                            0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_TX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT__SHIFT                                                0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__INVERT_OVRD_EN__SHIFT                                        0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN__SHIFT                                               0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__DATA_EN_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ__SHIFT                                                   0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                           0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD__SHIFT                                                   0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__LPD_OVRD_EN__SHIFT                                           0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE__SHIFT                                                0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__PSTATE_OVRD_EN__SHIFT                                        0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS__SHIFT                                         0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RX_DFE_BYPASS_OVRD_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_0__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__REF_LD_VAL_OVRD_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE__SHIFT                                                  0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                          0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH__SHIFT                                                 0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                         0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL__SHIFT                                            0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__VCO_LD_VAL_OVRD_EN__SHIFT                                    0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN__SHIFT                                        0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_2__DIV16P5_CLK_EN_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_TRACK_EN_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN__SHIFT                                            0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__CDR_SSC_EN_OVRD_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE__SHIFT                                               0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__DISABLE_OVRD_EN__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS__SHIFT                                       0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__VREG_CLK_BYPASS_OVRD_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN__SHIFT                                            0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__FLYOVER_EN_OVRD_EN__SHIFT                                    0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                                  0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_3__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_CTRL_RANGE_OVRD_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN__SHIFT                                      0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_UPDATE_EN_OVRD_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS__SHIFT                                         0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RX_DCC_BYPASS_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_IN_4__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LF_THRES_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_VAL__SHIFT                         0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_HF_THRES_OVRD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_VAL__SHIFT                   0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__SIGDET_LFPS_FILTER_EN_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_SIGDET_IN__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__CDR_VCO_CONFIG_OVRD_EN__SHIFT                              0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_VCO_IN__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_ATT_LVL_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN__SHIFT                                        0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_VGA_GAIN_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__EQ_CTLE_BOOST_OVRD_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_CTLE_POLE_OVRD_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE__SHIFT                                        0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_RATE_OVRD_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS__SHIFT                                        0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_BIAS_OVRD_EN__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__EQ_AFE_VCM_ADJ_OVRD_EN__SHIFT                             0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__EQ_DFE_TAP1_OVRD_EN__SHIFT                                0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP2_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3__SHIFT                                        0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3__EQ_DFE_TAP3_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP4_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5__SHIFT                                        0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_4__EQ_DFE_TAP5_OVRD_EN__SHIFT                                0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__ADAPT_STS_OVRD_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_VAL__SHIFT                                       0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__VALID_OVRD_EN__SHIFT                                        0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_OUT_0__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__INVERT__SHIFT                                                0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DATA_EN__SHIFT                                               0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__REQ__SHIFT                                                   0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__LPD__SHIFT                                                   0x4
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__PSTATE__SHIFT                                                0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RATE__SHIFT                                                  0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__WIDTH__SHIFT                                                 0xa
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__DIV16P5_CLK_EN__SHIFT                                        0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__RX_DFE_BYPASS__SHIFT                                         0xe
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_0__CDR_TRACK_EN__SHIFT                                          0xf
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__CDR_SSC_EN__SHIFT                                            0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__DISABLE__SHIFT                                               0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LF_THRES__SHIFT                                       0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_HF_THRES__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__SIGDET_LFPS_FILTER_EN__SHIFT                                 0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__FLYOVER_EN__SHIFT                                            0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_1__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_REF_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RX_DCC_CTRL_RANGE__SHIFT                                     0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_2__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RX_VCO_LD_VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_IN_3__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RX_CDR_VCO_CONFIG__SHIFT                               0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_ATT_LVL__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_VGA_GAIN__SHIFT                                        0x3
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_BOOST__SHIFT                                      0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__EQ_CTLE_POLE__SHIFT                                       0xc
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_DFE_TAP1__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_RATE__SHIFT                                        0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_BIAS__SHIFT                                        0xb
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1__EQ_AFE_VCM_ADJ__SHIFT                                     0xd
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_BIAS_TIA__SHIFT                                    0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_2__EQ_AFE_CTLE_ZERO__SHIFT                                   0xd
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__VALID__SHIFT                                                0x1
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__ADAPT_STS__SHIFT                                            0x2
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_ASIC_OUT_0__RESERVED_15_5__SHIFT                                        0x5
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_VAL__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RX_MISC_OVRD_EN__SHIFT                                       0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_MISC__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__EQ_DFE_EEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_5__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__EQ_DFE_EOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_6__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__EQ_DFE_DEL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_7__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOH_TAP1_OFST_OVRD_EN__SHIFT                       0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD__SHIFT                          0x7
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__EQ_DFE_DOL_TAP1_OFST_OVRD_EN__SHIFT                       0xd
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_8__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ__SHIFT                                              0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__EQ_IQ_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_9__RESERVED_15_9__SHIFT                                      0x9
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_BIAS_TIA_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO__SHIFT                                  0x6
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__EQ_AFE_CTLE_ZERO_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_10__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__EQ_AFE_CTLE_OFST_OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_11__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RX_P0_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BLEEDER_EN__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_AFE_EN__SHIFT                               0x1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_VREG_EN__SHIFT                          0x2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DIV16P5_CLK_EN__SHIFT                       0x3
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CLK_DCC_EN__SHIFT                           0x5
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DESER_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_CDR_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_FREQ_RST__SHIFT                             0x8
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CAL_RST__SHIFT                              0x9
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_VCO_CONTCAL_EN__SHIFT                           0xa
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_DIG_CLK_EN__SHIFT                               0xb
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_DFE_EN__SHIFT                               0xc
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RX_P0S_ANA_BYPASS_SLC_EN__SHIFT                        0xd
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RX_P1_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P0_ANA_BLEEDER_EN__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_AFE_EN__SHIFT                                 0x1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_VREG_EN__SHIFT                            0x2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DIV16P5_CLK_EN__SHIFT                         0x3
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_EN__SHIFT                                 0x4
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CLK_DCC_EN__SHIFT                             0x5
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DESER_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_CDR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_FREQ_RST__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CAL_RST__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_VCO_CONTCAL_EN__SHIFT                             0xa
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_DIG_CLK_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_DFE_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RX_P2_ANA_BYPASS_SLC_EN__SHIFT                          0xd
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_RATE_TIME__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_EN_TIME__SHIFT                               0x2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__FAST_RX_VREG_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0__RX_VREG_FAST_START_TIME__SHIFT                       0xa
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CDR_EN_TIME__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_EN_TIME__SHIFT                              0x5
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_DESER_DIS_TIME__SHIFT                             0x7
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__RX_CLK_DCC_EN_TIME__SHIFT                            0x9
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1__FAST_RX_CLK_DCC_EN__SHIFT                            0xf
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CLK_EN__SHIFT                                              0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DIG_CLK_EN__SHIFT                                          0x1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_FORCE_DAC_WRITE__SHIFT                                 0x2
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_DCC_DAC_WRITE_EN__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_SKIP_IQC_FSM__SHIFT                                        0x4
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_EQ_FORCE_DAC_WRITE__SHIFT                                  0x5
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RX_CAL_DAC_OVRD_GATE_EN__SHIFT                                0x6
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_CTL__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_RATE_IRQ__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RX_PWRSM_STATE__SHIFT                                      0x1
#define C20_PHY_CR1_LANEX_DIG_RX_PWRCTL_RX_STATUS__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT__SHIFT                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_FIXED_CNT_EN__SHIFT                   0x5
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_CNT_SHIFT__SHIFT                      0x6
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__INT_GAIN_CAL_BOUNCE_CNT__SHIFT                     0x9
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_BIN_HOLD__SHIFT                            0xc
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_INT_GAIN_HOLD__SHIFT                       0xd
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__DISABLE_COARSE_CALDONE__SHIFT                      0xe
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0__EXIT_BIN_SEARCH__SHIFT                             0xf
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_OVRD_SEL__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_FREQ_RST__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CAL_RST__SHIFT                              0x2
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__RX_VCO_CONTCAL_EN__SHIFT                           0x3
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DISABLE_INT_CAL_MODE__SHIFT                        0x4
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DPLL_CAL_UG__SHIFT                                 0x5
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT                                     0x9
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_START_VAL__SHIFT                         0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__FREG_TUNE_CAL_STEPS__SHIFT                         0xa
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_FREQ_TUNE_CAL__SHIFT                   0xe
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2__SKIP_RX_VCO_CAL__SHIFT                             0xf
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_UPDATE_TIME__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RX_VCO_CNTR_PWRUP_TIME__SHIFT                      0x4
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__FAST_RX_VCO_WAIT__SHIFT                            0xc
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0__RESERVED_15_13__SHIFT                              0xd
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_CNTR_SETTLE_TIME__SHIFT                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RX_VCO_STARTUP_TIME__SHIFT                         0x3
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1__RESERVED_15_10__SHIFT                              0xa
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_FREQ_TUNE__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_PD__SHIFT                              0xa
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_VCO_CNTR_EN__SHIFT                              0xb
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_STARTUP__SHIFT                              0xc
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CDR_VCO_EN__SHIFT                               0xd
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RX_ANA_CLK_EN__SHIFT                                   0xe
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FSM_STATE__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_FREQ_RST__SHIFT                                 0x4
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_RST__SHIFT                                  0x5
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CONTCAL_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RX_VCO_CAL_DONE__SHIFT                                 0x7
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__DPLL_FREQ_RST__SHIFT                                   0x8
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCO_CNTR_FINAL__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__VCOCLK_TOO_FAST__SHIFT                                 0xd
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_CORRECT__SHIFT                                  0xe
#define C20_PHY_CR1_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2__RX_VCO_UP__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL
#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__MODE__SHIFT                                                       0x0
#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__SYNC__SHIFT                                                       0x4
#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__BER_SEL__SHIFT                                                    0x5
#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_CTL__RESERVED_15_6__SHIFT                                              0x6
//C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR
#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__COUNT__SHIFT                                                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_LBERT_ERR__OV14__SHIFT                                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EDGE__SHIFT                                             0x2
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_POL__SHIFT                                              0x4
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__PHDET_EN_PR_MODE__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__DTB_SEL__SHIFT                                                0x6
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_0__RESERVED_15_10__SHIFT                                         0xa
//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT0__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_1__SSC_OFF_CNT1__SHIFT                                           0xa
//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT0__SHIFT                                            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_2__SSC_ON_CNT1__SHIFT                                            0x9
//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG0__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_PHUG1__SHIFT                                          0x3
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__SSC_OFF_FRUG0__SHIFT                                          0x6
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__OVRD_DPLL_GAIN__SHIFT                                         0x9
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__PHUG_OVRD_VALUE__SHIFT                                        0xa
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_3__FRUG_OVRD_VALUE__SHIFT                                        0xd
//C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_OFF_FRUG1__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG0__SHIFT                                           0x3
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_FRUG1__SHIFT                                           0x6
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG0__SHIFT                                           0x9
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__SSC_ON_PHUG1__SHIFT                                           0xc
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_CDR_CTL_4__RESERVED_15_15__SHIFT                                         0xf
//C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__PHUG_VALUE__SHIFT                                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__FRUG_VALUE__SHIFT                                                  0x3
#define C20_PHY_CR1_LANEX_DIG_RX_CDR_STAT__RESERVED_15_6__SHIFT                                               0x6
//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__VAL__SHIFT                                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ__RESERVED_15_14__SHIFT                                             0xe
//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__FREQ_BOUND_EN__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__UPPER_FREQ_BOUND__SHIFT                                   0x1
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_0__RESERVED_15_11__SHIFT                                     0xb
//C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__LOWER_FREQ_BOUND__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_RX_DPLL_FREQ_BOUND_1__RESERVED_15_10__SHIFT                                     0xa
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TOP_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__N_TGG_ASM1__SHIFT                                        0xa
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__START_ASM1__SHIFT                                        0xe
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__N_WAIT_ASM1__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_RXCLK_SEL__SHIFT                                    0x7
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_VAL__SHIFT                                0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__CTLE_POLE_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__DFE_T1_ANA_DIS__SHIFT                                    0xb
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__ADPT_AUTO_GLCM__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_0__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__TGG_PTTRN_1__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__CTLE_EN__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__VGA_EN__SHIFT                                            0x5
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ATT_EN__SHIFT                                            0x6
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__DFE_EN__SHIFT                                            0x7
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHE_EN__SHIFT                                          0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__EYEHO_EN__SHIFT                                          0xd
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__TGG_EN__SHIFT                                            0xe
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3__ESL_TWICE_DSL__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__CTLE_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__VGA_TH__SHIFT                                            0x4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE1_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4__DFE2_TH__SHIFT                                           0xc
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE3_TH__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE4_TH__SHIFT                                           0x4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__DFE5_TH__SHIFT                                           0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5__TH_OFFSET__SHIFT                                         0xc
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__CTLE_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_MU__SHIFT                                            0x3
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_MU__SHIFT                                            0x6
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT__SHIFT                                       0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__VGA_SAT_CNT_STICKY__SHIFT                                0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6__ATT_LOW_TH__SHIFT                                        0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_MIN_SAT__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_HIGH__SHIFT                                      0x4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__VGA_LEV_LOW__SHIFT                                       0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7__RESERVED_15_12__SHIFT                                    0xc
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE1_MU__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE2_MU__SHIFT                                           0x3
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE3_MU__SHIFT                                           0x6
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE4_MU__SHIFT                                           0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__DFE5_MU__SHIFT                                           0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLE_ADPT_INIT__SHIFT                                 0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9__ERR_SLO_ADPT_INIT__SHIFT                                 0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_ATT__SHIFT                                    0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_VGA__SHIFT                                    0x1
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_BOOST__SHIFT                             0x2
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_CTLE_POLE__SHIFT                              0x3
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP1__SHIFT                                   0x4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_RX_DCC__SHIFT                                      0x5
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_RATE__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_VCM_ADJ__SHIFT                            0x7
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_MT__SHIFT                            0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_TAP2__SHIFT                                   0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_CTLE_ZERO__SHIFT                          0xa
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RST_ADPT_AFE_BIAS_TIA__SHIFT                           0xb
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG__RESERVED_15_12__SHIFT                                  0xc
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ATT_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_DONE__SHIFT                                         0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__ASM1_STATE__SHIFT                                        0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__DAC_CTRL_STATE__SHIFT                                    0xd
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ATT_STATUS__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__VGA_ADPT_CODE__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__ASM1_DONE__SHIFT                                         0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_VGA_STATUS__RESERVED_15_10__SHIFT                                    0xa
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_BOOST_ADPT_CODE__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__CTLE_POLE_ADPT_CODE__SHIFT                              0xa
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__ASM1_DONE__SHIFT                                        0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__DFE_TAP1_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__ASM1_DONE__SHIFT                                    0xd
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS__RESERVED_15_14__SHIFT                               0xe
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__DFE_TAP2_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__DFE_TAP3_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__DFE_TAP4_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__DFE_TAP5_ADPT_CODE__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__ASM1_DONE__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS__RESERVED_15_13__SHIFT                               0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT    0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                   0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                    0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RX_ANA_SLICER_CTRL_E__SHIFT                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN__RESERVED_15_4__SHIFT                            0x4
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RX_ANA_SLICER_CTRL_O__SHIFT                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD__RESERVED_15_4__SHIFT                             0x4
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__E_SLO_LVL__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_ODD_LEVEL__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__E_SLE_LVL__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_EVEN_LEVEL__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESET_ASM1__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_RESET__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__CTLE_T1_WT__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_10__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__VAL__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__OVRD_EN__SHIFT                          0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                    0x9
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__VAL__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_PHASE_CM_IDAC_OFST__RESERVED_15_9__SHIFT                      0x9
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__OVRD_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_DATA_CM_IDAC_OFST__RESERVED_15_9__SHIFT                       0x9
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__VAL__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__OVRD_EN__SHIFT                         0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_DIFF_IDAC_OFST__RESERVED_15_9__SHIFT                   0x9
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__VAL__SHIFT                               0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__OVRD_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_DCC_BYPASS_CM_IDAC_OFST__RESERVED_15_9__SHIFT                     0x9
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_AFE_DFE_SETTLE__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__FAST_SSM_DAC_SETTLE__SHIFT                            0x1
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_RX_FAST_FLAGS__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MIN_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__CTLE_MAX_SAT__SHIFT                                     0x5
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_11__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__DFE1_MAX_SAT__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_12__RESERVED_15_7__SHIFT                                    0x7
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_TH_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DAC_SEL__SHIFT                                    0x4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__SSM_DEST_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__START_SSM__SHIFT                                      0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_0__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUM_LIN_STEPS__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__NUN_BIN_STEPS__SHIFT                                  0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__LIN_STEP__SHIFT                                       0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_1__RESERVED_15_14__SHIFT                                 0xe
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_DAC_CODE__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__INIT_BIN_STEP__SHIFT                                  0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__DISABLE_BIN_HOLD__SHIFT                               0xb
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__SSM_TH__SHIFT                                         0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_2__RESERVED_15_15__SHIFT                                 0xf
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_INIT_WAIT__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__RESERVED__SHIFT                                       0xc
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__LPFBYP_EN__SHIFT                                      0xd
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__STICKY_EN__SHIFT                                      0xe
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_3__SSM_DIR__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_SSM_CFG_4__SSM_N_WAIT_LPFBYP__SHIFT                              0x8
//C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__DAC_CODE__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__SSM_DONE__SHIFT                                      0x8
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RATE_REQ__SHIFT                              0x9
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__ABORTED_RST_REQ__SHIFT                               0xa
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__FSM_STATE__SHIFT                                     0xb
#define C20_PHY_CR1_LANEX_DIG_RX_ADPTCTL_SSM_FINAL_CODE__RESERVED_15_14__SHIFT                                0xe
//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_LD_VAL__SHIFT                                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_1__SC1_START__SHIFT                                              0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_DATA_MSK__DATA_MSK_15_0__SHIFT                                          0x0
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_MSK_CR1A_4_0__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__PTTRN_CR1A_4_0__SHIFT                                       0x5
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__DATA_MSK_19_16__SHIFT                                       0xa
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL0__SCOPE_DLY__SHIFT                                            0xe
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_MSK_CR1B_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1B_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__PTTRN_CR1A_ADPT_EN__SHIFT                                   0xb
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL1__RESERVED_15_12__SHIFT                                       0xc
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__RESERVED_0__SHIFT                                            0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SHFT_SEL__SHIFT                                         0x1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_SRC_SEL__SHIFT                                          0x3
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__CORR_MODE_EN__SHIFT                                          0x5
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SHFT_SEL__SHIFT                                         0x6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_SRC_SEL__SHIFT                                          0xa
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__STAT_RXCLK_SEL__SHIFT                                        0xd
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SC_TIMER_MODE__SHIFT                                         0xe
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL0__SKIP_EN__SHIFT                                               0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_0_EN__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_1_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_2_EN__SHIFT                                         0x2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_3_EN__SHIFT                                         0x3
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_4_EN__SHIFT                                         0x4
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_5_EN__SHIFT                                         0x5
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CNT_6_EN__SHIFT                                         0x6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__CORR_SHFT_SEL_VGA__SHIFT                                     0x7
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__SC_PAUSE__SHIFT                                              0x9
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__STAT_CLK_EN__SHIFT                                           0xa
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__DATA_DLY_SEL__SHIFT                                          0xb
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_LOSS_CLR__SHIFT                                          0xd
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL1__VLD_CTL__SHIFT                                               0xe
//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1__SHIFT                                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1__SMPL_CNT1_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_29_15__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_29DN15__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_44_30__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT1_44DN30__SMPL_CNT1_DONE__SHIFT                                 0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__STAT_CNT_0__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_0__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__STAT_CNT_1__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_1__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__STAT_CNT_2__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_2__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__STAT_CNT_3__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_3__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__STAT_CNT_4__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_4__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__STAT_CNT_5__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_5__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__STAT_CNT_6__SHIFT                                           0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_6__SMPL_CNT1_DONE__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__PRECHRGE_CNT__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__REF_DIV_CNT__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__DIV1_CLK_SEL__SHIFT                                   0x6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__COMP_CLK_EN__SHIFT                                    0x7
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__PTTRN_CR1A_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL2__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__PTTRN_MSK_CR1A_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL3__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__PTTRN_CR1B_19_5__SHIFT                                      0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL4__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__PTTRN_MSK_CR1B_19_5__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL5__RESERVED_15_15__SHIFT                                       0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DATA_DLY_SEL_2__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_DLY_2__SHIFT                                           0x1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__DISABLE_SAMPLE_COUNT__SHIFT                                  0x2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__ENABLE_AUTO_GLCM__SHIFT                                      0x3
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__SCOPE_FIFO_RST_EN__SHIFT                                     0x4
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__INVERT_CORR_VGA_EN__SHIFT                                    0x5
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__FREEZE_STAT_CNT__SHIFT                                       0x6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__STAT_CNT_FREEZE_SEL__SHIFT                                   0x7
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CTL2__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__SC1_STOP__SHIFT                                              0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_STOP__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_EN__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_MSK_CR2A_4_0__SHIFT                                   0x1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__PTTRN_CR2A_4_0__SHIFT                                       0x6
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_MATCH_CTL6__RESERVED_15_11__SHIFT                                       0xb
//C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__STAT_CNT_N_SHD__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_STAT_CNT_N_SHD__SMPL_CNT1_DONE__SHIFT                                   0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2__SHIFT                                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_SMPL_CNT2__SMPL_CNT2_DONE__SHIFT                                        0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_14_0__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_1__SC1_LD_VAL_EXT_EN__SHIFT                                  0xf
//C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__SC1_LD_VAL_EXT_29_15__SHIFT                               0x0
#define C20_PHY_CR1_LANEX_DIG_RX_STAT_LD_VAL_EXT_2__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__BYPASS__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_RESET_ADJUST__DATA__SHIFT                                            0x8
//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__STEP_SIZE__SHIFT                                             0x0
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV1__SHIFT                                             0x3
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIV2__SHIFT                                             0x4
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__JUMP_DIVN__SHIFT                                             0x5
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__BYPASS_EN__SHIFT                                             0x6
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__DATA_EN__SHIFT                                               0x7
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__USE_DFE_BYPASS__SHIFT                                        0x8
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_CONFIG__RESERVED_15_9__SHIFT                                         0x9
//C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RX_IQC_FSM_STATE__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_RX_IQC_CTL_STAT__RESERVED_15_4__SHIFT                                           0x4
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV16P5_CLK_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE__SHIFT                                 0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DATA_RATE_OVRD_EN__SHIFT                         0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN__SHIFT                                   0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DIV4_EN_OVRD_EN__SHIFT                           0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_TAPS_EN_OVRD_EN__SHIFT                       0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_DFE_EN_OVRD_EN__SHIFT                            0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_BYPASS_SLC_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST__SHIFT                                 0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CTL_OVRD_OUT__RX_ANA_ASYNC_RST_OVRD_EN__SHIFT                         0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_AFE_EN_OVRD_EN__SHIFT                          0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START__SHIFT                         0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_VREG_FAST_START_OVRD_EN__SHIFT                 0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_VREG_EN_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                              0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_DCC_EN_OVRD_EN__SHIFT                      0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN__SHIFT                                  0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CLK_EN_OVRD_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_CDR_EN_OVRD_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN__SHIFT                             0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_DESERIAL_EN_OVRD_EN__SHIFT                     0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                              0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_0__RX_ANA_BLEEDER_EN_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC__SHIFT                                    0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_MISC_OVRD_EN__SHIFT                            0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS__SHIFT                         0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_VREG_CLK_BYPASS_OVRD_EN__SHIFT                 0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                             0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RX_ANA_WORD_CLK_EN_OVRD_EN__SHIFT                     0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_PWR_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RX_ANA_SIGDET_CAL_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_CAL_EN__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RX_ANA_SIGDET_HF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_HF_CAL__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE__SHIFT                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RX_ANA_SIGDET_LF_CAL_TUNE_OVRD_EN__SHIFT               0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SIGDET_LF_CAL__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_VCO_EN_OVRD_EN__SHIFT                      0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP__SHIFT                             0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_CDR_STARTUP_OVRD_EN__SHIFT                     0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_PD_OVRD_EN__SHIFT                     0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN__SHIFT                             0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_EN_OVRD_EN__SHIFT                     0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK__SHIFT                            0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RX_ANA_VCO_CNTR_CLK_OVRD_EN__SHIFT                    0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_0__RESERVED_15_10__SHIFT                                 0xa
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RX_ANA_CDR_VCO_CONFIG_OVRD_EN__SHIFT                  0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_1__RESERVED_15_13__SHIFT                                 0xd
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE_CLK__SHIFT                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_ANA_CDR_FREQ_TUNE__SHIFT                           0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RX_CDR_FREQ_TUNE_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VCO_OVRD_OUT_2__RESERVED_15_12__SHIFT                                 0xc
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXA_SEL__SHIFT                                     0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MUXB_SEL__SHIFT                                     0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_LPFBYP_EN__SHIFT                                    0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_SHORT_EN__SHIFT                                     0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_SLICER_CAL_EN__SHIFT                                    0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_MODE__SHIFT                                         0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_0__RX_ANA_CAL_COMP_EN__SHIFT                                      0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_CAL_LPFBYP_EN_OVRD_EN__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RX_ANA_SLICER_CAL_RANGE__SHIFT                                 0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_CAL_1__RESERVED_15_2__SHIFT                                           0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_PRANGE_SEL__SHIFT                     0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RX_ANA_CAL_VDAC_DERANGE_SEL__SHIFT                    0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RX_ANA_CAL_DAC_CTRL__SHIFT                                  0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL__RESERVED_15_8__SHIFT                                        0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_VAL__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_OVRD_EN__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_ANA_AFE_TRIM_THRESH__SHIFT                              0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RX_AFE_TRIM_EN_R__SHIFT                                    0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_RTRIM__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RX_CAL_DAC_CTRL_OVRD__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_OVRD__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RX_ANA_CAL_DAC_CTRL_SEL__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DAC_CTRL_SEL__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE__SHIFT          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RX_ANA_DCC_CAL_DAC_CTRL_RANGE_OVRD_EN__SHIFT  0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_DCC_CAL_DAC_CTRL_RANGE__RESERVED_15_5__SHIFT                          0x5
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_ATT_LVL_OVRD_EN__SHIFT                      0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_VGA_GAIN_OVRD_EN__SHIFT                     0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE__SHIFT                                 0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RX_ANA_AFE_RATE_OVRD_EN__SHIFT                         0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_0__RESERVED_15_13__SHIFT                                  0xd
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_POLE_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST__SHIFT                           0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_CTLE_BOOST_OVRD_EN__SHIFT                   0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT__SHIFT                              0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_BIAS_MT_OVRD_EN__SHIFT                      0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ__SHIFT                              0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_1__RX_ANA_AFE_VCM_ADJ_OVRD_EN__SHIFT                      0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_EN__SHIFT                                         0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RX_ANA_SCOPE_CLK_SEL__SHIFT                                    0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SCOPE__RESERVED_15_3__SHIFT                                           0x3
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_E__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_O__SHIFT                              0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RX_ANA_SLICER_CTRL_OVRD_EN__SHIFT                        0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_SLICER_CTRL__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_EN__SHIFT                                               0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__SENSE_SEL__SHIFT                                              0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_CLK_VRO_ALLON__SHIFT                                       0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_VAL__SHIFT                              0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__EN_IQSYNC_BYPASS_OVRD_EN__SHIFT                               0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_VAL__SHIFT                              0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__CKDRV_IQSYNC_RST_OVRD_EN__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQ__RESERVED_15_7__SHIFT                                          0x7
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__EN__SHIFT                                           0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYP_OVRD__RESERVED_15_9__SHIFT                                0x9
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__VAL__SHIFT                                 0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                  0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_BYPASS_ADJUST_CLK__RESERVED_15_2__SHIFT                       0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__EN__SHIFT                                          0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_OVRD__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__VAL__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__SELF_CLEAR_DISABLE__SHIFT                    0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_IQC_DATA_ADJUST_CLK__RESERVED_15_2__SHIFT                         0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RX_ANA_CAL_DAC_CTRL_EN__SHIFT                    0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__DAC_CTRL_SELF_CLEAR_DISABLE__SHIFT               0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CAL_DAC_CTRL_EN__RESERVED_15_2__SHIFT                             0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN__SHIFT                               0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_CLK_EN_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL__SHIFT                                  0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_SEL_OVRD_EN__SHIFT                          0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RX_LBK_DCC_CAL_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_LOOPBACK_CTRL__RESERVED_15_5__SHIFT                               0x5
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN__SHIFT                        0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__UPDATE_SELF_CLEAR_DISABLE__SHIFT                   0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RX_ANA_AFE_UPDATE_EN_OVRD_EN__SHIFT                0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_AFE_UPDATE_EN__RESERVED_15_3__SHIFT                               0x3
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_DFE_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_BYP_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_PHS_SAMP_SEL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_CODE__SHIFT                               0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RX_TERM_OVRD_EN__SHIFT                            0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_OVRD_OUT__RESERVED_15_7__SHIFT                              0x7
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RX_TERM_CLK_SELF_CLEAR_DISABLE__SHIFT         0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_TERM_CODE_CLK_OVRD_OUT__RESERVED_15_2__SHIFT                          0x2
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DESERIAL_EN_LPBK__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_EN__SHIFT                                      0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_DCC_EN__SHIFT                                  0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_VREG_CLK_BYPASS__SHIFT                             0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BLEEDER_EN__SHIFT                                  0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_CLK_VREG_EN__SHIFT                                 0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_AFE_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_SEL__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_LOOPBACK_CLK_EN__SHIFT                             0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_BYPASS_SLC_EN__SHIFT                               0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_EN__SHIFT                                      0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DFE_TAPS_EN__SHIFT                                 0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DIV4_EN__SHIFT                                     0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_0__RX_ANA_DATA_RATE__SHIFT                                   0xd
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CKDRV_IQSYNC_RST__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_EN_IQSYNC_BYPASS__SHIFT                            0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CAL_LPFBYP_EN__SHIFT                               0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_PHUG__SHIFT                                    0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_EN__SHIFT                                      0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_EN__SHIFT                                 0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VCO_CNTR_PD__SHIFT                                 0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_STARTUP__SHIFT                                 0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_CDR_VCO_EN__SHIFT                                  0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_VREG_FAST_START__SHIFT                             0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_FLYOVER_EN__SHIFT                                  0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_ASYNC_RST__SHIFT                                   0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RX_ANA_WORD_CLK_EN__SHIFT                                 0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_OUT_1__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_CAL_RESULT__SHIFT                                   0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_SCOPE_DATA__SHIFT                                   0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RX_ANA_VCO_CNTR__SHIFT                                     0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_STAT_IN_0__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO__SHIFT                            0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_CTLE_ZERO_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA__SHIFT                             0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RX_ANA_AFE_BIAS_TIA_OVRD_EN__SHIFT                     0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_AFE_OVRD_IN_2__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_1_0__SHIFT                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_BYP_SAMP_SEL_REG__SHIFT                            0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_BYP_SAMP_SEL__SHIFT                           0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_PHS_SAMP_SEL_REG__SHIFT                            0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_PHS_SAMP_SEL__SHIFT                           0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DFE_SAMP_SEL_REG__SHIFT                            0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DFE_SAMP_SEL__SHIFT                           0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_MEAS_ATB_CAL_VREF_2__SHIFT                         0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_AFE_RATE_REG__SHIFT                                0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_WORD_CLK_EN_REG__SHIFT                             0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_WORD_CLK_EN__SHIFT                            0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_OVRD_DCCANDAFE_EN__SHIFT                           0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG00__RX_ANA_DCC_EN_REG__SHIFT                                  0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_ACJT_EN__SHIFT                                0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_ACJT_EN_REG__SHIFT                                 0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_CLK_EN__SHIFT                                 0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_CLK_EN_REG__SHIFT                                  0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_SIGDET_HF_EN__SHIFT                           0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_SIGDET_HF_EN_REG__SHIFT                            0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_PWRON__SHIFT                                  0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_PWRON_REG__SHIFT                                   0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_VP_I__SHIFT                               0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MASTER_ATB_EN_I__SHIFT                             0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_BYPASS_SLC_EN_REG__SHIFT                           0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_OVRD_BYPASS_SLC_EN__SHIFT                          0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RESERVED_12_12__SHIFT                                     0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG01__RX_ANA_MEAS_ATB_CAL_MUX_I__SHIFT                          0xd
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_RX_9_6__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_O__SHIFT                              0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_MEAS_ATB_SUM_E__SHIFT                              0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_ODD_REG__SHIFT                               0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_PHDET_EVEN_REG__SHIFT                              0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_SIGDET_LF_EN__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_SIGDET_LF_EN_REG__SHIFT                            0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DFE_EN_REG__SHIFT                                  0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_DES_EN__SHIFT                                 0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_DESERIAL_EN_REG__SHIFT                             0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_OVRD_LOOPBACK_EN__SHIFT                            0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG02__RX_ANA_LOOPBACK_EN_REG__SHIFT                             0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_RX_LOOPBACK_CLK_EN__SHIFT                     0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_LOOPBACK_CLK_EN_REG__SHIFT                      0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_LOOPBACK_CLK_SEL_REG__SHIFT                        0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_SIGDET_VREF_EXT_EN_REG__SHIFT                   0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ATT_PULLDN_EN__SHIFT                                   0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_SHORT_EN_REG__SHIFT                                0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_OVRD_SHORT_EN__SHIFT                               0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_FRC_ATB_CAL_VREF_1_0__SHIFT                        0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG03__RX_ANA_RX_AFE_OVRD_FPK__SHIFT                             0xa
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_FRC_ATB_CAL_VREF_2__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_RX_5_0__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_ATB_FRC_VLOS__SHIFT                                0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG04__RX_ANA_MEAS_ATB_VREG_I_7_0__SHIFT                         0x8
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_DFE_TAPS_EN_REG__SHIFT                             0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_PWRON_TAPS__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_AFE_OVRD_RTRIM_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_FRC_ATB_CAL_VREF_4_3__SHIFT                        0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_GD_EN_REG__SHIFT                           0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_GD_EN__SHIFT                          0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_RX_TERM_DC_EN_REG__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_OVRD_RX_TERM_DC_EN__SHIFT                          0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RESERVED_12_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG05__RX_ANA_MEAS_ATB_RX_12_10__SHIFT                           0xd
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREF_CAL_SEL_N_REG__SHIFT                          0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_VCO_ATB_REG_6_0__SHIFT                        0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_VREG_VCO_BYPASS_REG__SHIFT                         0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_IQC_VREF_SEL__SHIFT                           0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RESERVED_10_10__SHIFT                                     0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_MEAS_ATB_VREG_I_8__SHIFT                           0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_FAST_START_REG__SHIFT                              0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVRD_FAST_START__SHIFT                             0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_VCO_REG__SHIFT                     0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG06__RX_ANA_OVERRIDE_REGREF_IQC_I__SHIFT                       0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG__SHIFT                              0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_RX_AFE_OVRD_ICTRL__SHIFT                           0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_OVRD_AFE_EN__SHIFT                                 0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_AFE_PD_NC_DIS__SHIFT                               0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG07__RX_ANA_VREG_BOOST_REG_11_8__SHIFT                         0xc
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_RX_SIGDET_HF_BIAS_SEL__SHIFT                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_BIAS_CURR_MODE_REG__SHIFT                          0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_RING_CTRL_REG__SHIFT                      0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_CMP_TRIM_REG__SHIFT                        0x5
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_GAIN_CTRL_REG__SHIFT                       0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_CP_MODE_REG__SHIFT                            0x8
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_RING_CTRL_REG__SHIFT                          0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_OVERRIDE_REGREF_VREG_REG__SHIFT                    0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RX_ANA_VREG_FB_DIV_CTRL_REG__SHIFT                        0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG08__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ANA_LOOPBACK_RATE_SEL__SHIFT                           0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_ATT_VCM_SEL__SHIFT                                     0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL__SHIFT                                 0x3
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_CM_SEL_SCOPE__SHIFT                           0x6
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_SUM_CM_SEL__SHIFT                                      0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_DEB__SHIFT                             0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_SCOPE__SHIFT                           0xd
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RX_CAL_VDAC_BYP_CM_PH__SHIFT                              0xe
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG09__RESERVED_15_15__SHIFT                                     0xf
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_ON_REG__SHIFT                                       0x0
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_INV_POLARITY_REG__SHIFT                             0x1
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_RESP_REG__SHIFT                                0x2
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RX_SQ_CTRL_TRESH_REG__SHIFT                               0x4
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__PWM_CLK_SEL_REG__SHIFT                                    0x7
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__PWM_EN_REG__SHIFT                                         0x9
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_DFE_RANGE__SHIFT                                      0xa
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SLC_SCOPE_RANGE__SHIFT                                    0xb
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__SCOPE_SEL_REF__SHIFT                                      0xc
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG10__RESERVED_15_14__SHIFT                                     0xe
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG11__RESERVED_15_0__SHIFT                                      0x0
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG0_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD
#define C20_PHY_CR1_LANEX_DIG_ANA_XF_RX_ANA_CREG1_OVRD__RESERVED_15_0__SHIFT                                  0x0
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_TX2RX_SER_LB_EN_OVRD_EN__SHIFT                0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM__SHIFT                               0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__LANE_LINK_NUM_OVRD_EN__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_OVRD_IN_0__RESERVED_15_9__SHIFT                               0x9
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RX2TX_PAR_LB_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__TX2RX_SER_LB_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__LANE_LINK_NUM__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_LANE_IN_0__RESERVED_15_6__SHIFT                                    0x6
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY__SHIFT                                          0x9
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__CLK_RDY_OVRD_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__BEACON_EN_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN__SHIFT                                          0xd
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                  0xe
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                       0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ__SHIFT                                        0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__DETRX_REQ_OVRD_EN__SHIFT                                0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                      0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                        0x9
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xc
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_2__RESERVED_15_14__SHIFT                                   0xe
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_IN_3__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__BEACON_EN__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MPLL_EN__SHIFT                                               0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLA_STATE__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__MSTR_MPLLB_STATE__SHIFT                                      0x9
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__DETRX_REQ__SHIFT                                             0xa
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__CLK_DSKW_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__LANE2LANE_DSKW_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_FORCE_EN__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RECAL_SKIP_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_IN_2__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__DETRX_RESULT_OVRD_EN__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__WIDTH__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__ALIGN_WIDE_XFER_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__MPLLB_SEL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VREG_TX_BYPASS__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__VBOOST_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__IBOOST_LVL__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__DRV_EN_KR__SHIFT                                       0xe
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_0__OFFCAN_CONT__SHIFT                                     0xf
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__MISC__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_CTRL_RANGE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__DCC_BYPASS__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_1__TERM_CTRL__SHIFT                                       0xd
//C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__TX_UNIQUE_ID__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL__SHIFT                                         0x9
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLLB_SEL_OVRD_EN__SHIFT                                 0xa
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN__SHIFT                                           0xb
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__MPLL_EN_OVRD_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_1__RESERVED_15_13__SHIFT                                    0xd
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLA_STATE_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__MASTER_MPLLB_STATE_OVRD_EN__SHIFT                        0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__TX_CLK_EN__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__LANE2LANE_DSKW_EN_OVRD_EN__SHIFT                         0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__CLK_DSKW_EN_OVRD_EN__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_IN_2__RESERVED_15_9__SHIFT                                     0x9
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__LANE_NUMBER__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_LANE_NUMBER__RESERVED_15_3__SHIFT                                   0x3
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_IN_0__RESERVED_15_2__SHIFT                                          0x2
//C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESET_RTN_REQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RESET_RTN_REQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RATE_IRQ_MSK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_REQ_IRQ_MSK__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_RESET_IRQ_MSK__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_EN_IRQ_MSK__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RX2TX_PAR_LB_DIS_IRQ_MSK__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RTUNE_IRQ_MSK__SHIFT                                    0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__TX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__LANE_XCVR_MODE_IRQ_MSK__SHIFT                           0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_MASK__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RX2TX_PAR_LB_IRQ_EN__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_RATE_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RTUNE_IRQ_EN__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__TX_TERM_CTRL_IRQ_EN__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__LANE_XCVR_MODE_IRQ_EN__SHIFT                        0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__TX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__TX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__TX_RESET_IRQ__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__TX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__TX_REQ_IRQ__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__TX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RX2TX_PAR_LB_EN_IRQ__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RX2TX_PAR_LB_EN_IRQ_CLR__SHIFT           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_EN_IRQ_CLR__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RX2TX_PAR_LB_DIS_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RX2TX_PAR_LB_DIS_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RX2TX_PAR_LB_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RTUNE_IRQ__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RTUNE_CLR__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_RTUNE_IRQ_CLR__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__TX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__TX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_TX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__LANE_XCVR_MODE_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__LANE_XCVR_MODE_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P2_ALLOW_RXDET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P1_ALLOW_RXDET__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0S_ALLOW_RXDET__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_P0_ALLOW_RXDET__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_RATE_IRQ_EN__SHIFT                                   0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MPLLB_SEL_IRQ_EN__SHIFT                              0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_MISC_IRQ_EN__SHIFT                                   0x7
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x9
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0xa
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__TX_CAL_DONE_IRQ_EN__SHIFT                                    0xb
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FSM_CTL__RESERVED_15_12__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__TX_CLK_SEL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_CLK_CTL__RESERVED_15_5__SHIFT                                         0x5
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__TX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__TX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_TERM_CODE__RESERVED_15_10__SHIFT                                      0xa
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__DONE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_FW_PWRUP_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__TX_MPLLA_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLA_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__TX_MPLLB_RSTR_CAL_EN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_CTL_MPLLB_RSTR_CAL_CTL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_VAL__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_VAL__SHIFT                   0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_OVRD_EN__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_VAL__SHIFT               0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_RX2TX_PAR_LB_EN_OVRD_EN__SHIFT                0x4
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLA_EN_IN_OVRD_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__LANE_MPLLB_EN_IN_OVRD_EN__SHIFT                    0x6
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_IN_0__RESERVED_15_7__SHIFT                               0x7
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_VAL__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_VAL__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLA_EN_OUT_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__LANE_MPLLB_EN_OUT_OVRD_EN__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_OVRD_OUT_0__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLA_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__MPLLB_STATE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__SUP_STATE_OVRD_EN__SHIFT                            0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_OVRD_IN_0__RESERVED_15_3__SHIFT                                0x3
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLA_STATE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__MPLLB_STATE__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_0__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__TX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__LANE_RTUNE_REQ__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RTUNE_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_SUP_IN_1__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__LANE_RTUNE_ACK__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_TX_PMA_XF_LANE_RTUNE_CTL_1__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                    0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                   0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD__SHIFT                                              0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                      0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN__SHIFT                                          0x5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__DATA_EN_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__INVERT_OVRD_EN__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN__SHIFT                                       0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__CDR_SSC_EN_OVRD_EN__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_REQ_OVRD_EN__SHIFT                                0xc
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG__SHIFT                                    0xd
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__ADAPT_IN_PROG_OVRD_EN__SHIFT                            0xe
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IQ_OVRD_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG__SHIFT                                   0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_IN_PROG_OVRD_EN__SHIFT                           0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR__SHIFT                               0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__MARGIN_ERROR_CLEAR_OVRD_EN__SHIFT                       0xb
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN__SHIFT                                   0xc
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_FORCE_EN_OVRD_EN__SHIFT                           0xd
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_2__RECAL_SKIP_EN_OVRD_EN__SHIFT                            0xf
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__MARGIN_VDAC_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL__SHIFT                                   0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RECAL_BANK_SEL_OVRD_EN__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__LOOPBACK_SEL_OVRD_EN__SHIFT                             0xe
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_3__RESERVED_15_15__SHIFT                                   0xf
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__CNTX_SEL_OVRD_EN__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_IN_4__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESET__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__REQ__SHIFT                                                   0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_0__RESERVED_15_2__SHIFT                                         0x2
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__PSTATE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__LPD__SHIFT                                                   0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__DATA_EN__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__INVERT__SHIFT                                                0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__CDR_SSC_EN__SHIFT                                            0x5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_REQ__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__ADAPT_IN_PROG__SHIFT                                         0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__MARGIN_IQ__SHIFT                                             0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_1__RESERVED_15_15__SHIFT                                        0xf
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_VDAC__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_IN_PROG__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__MARGIN_ERROR_CLEAR__SHIFT                                    0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RECAL_BANK_SEL__SHIFT                                        0xb
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_2__RESERVED_15_13__SHIFT                                        0xd
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__CNTX_SEL__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_IN_3__RESERVED_15_8__SHIFT                                         0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OVRD_OUT_0__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__ACK__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_OUT_0__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_ATT_LVL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_VGA_GAIN__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_OFST_SEL__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_BOOST__SHIFT                                   0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_0__EQ_CTLE_POLE__SHIFT                                    0xe
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_CTLE_ZERO__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_RATE__SHIFT                                     0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS_TIA__SHIFT                                 0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_BIAS__SHIFT                                     0xb
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_1__EQ_AFE_VCM_ADJ__SHIFT                                  0xd
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__EQ_DFE_TAP1__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_2__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DFE_BYPASS__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_SEL__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__ADAPT_MODE__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__MISC__SHIFT                                            0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_3__DELTA_IQ__SHIFT                                        0xc
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__CDR_VCO_CONFIG__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_4__DCC_CTRL_RANGE__SHIFT                                  0xc
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__RATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__REF_LD_VAL__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__DIV16P5_CLK_EN__SHIFT                                  0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_5__CDR_PPM_MAX__SHIFT                                     0xb
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__WIDTH__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_6__VCO_LD_VAL__SHIFT                                      0x3
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LF_THRESHOLD__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_HF_THRESHOLD__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__SIGDET_LFPS_FILTER_EN__SHIFT                           0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__TERM_CTRL__SHIFT                                       0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__DCC_BYPASS__SHIFT                                      0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__VREG_CLK_BYPASS__SHIFT                                 0xb
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__ADAPT_CONT__SHIFT                                      0xc
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__OFFCAN_CONT__SHIFT                                     0xd
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_7__RESERVED_15_14__SHIFT                                  0xe
//C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__UNIQUE_ID__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PCS_XF_CNTX_CFG_8__RESERVED_15_10__SHIFT                                  0xa
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESET_OVRD_EN__SHIFT                                     0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__REQ_OVRD_EN__SHIFT                                       0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_0__RESERVED_15_4__SHIFT                                     0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__PSTATE_OVRD_EN__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD__SHIFT                                               0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__LPD_OVRD_EN__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE__SHIFT                                              0x5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RATE_OVRD_EN__SHIFT                                      0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH__SHIFT                                             0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__WIDTH_OVRD_EN__SHIFT                                     0xc
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS__SHIFT                                        0xd
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__DFE_BYPASS_OVRD_EN__SHIFT                                0xe
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_1__RESERVED_15_15__SHIFT                                    0xf
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__ADAPT_REQ_OVRD_EN__SHIFT                                 0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ__SHIFT                                          0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__DELTA_IQ_OVRD_EN__SHIFT                                  0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_IN_2__RESERVED_15_7__SHIFT                                     0x7
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESET__SHIFT                                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__REQ__SHIFT                                                    0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__DELTA_IQ__SHIFT                                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_IN_0__RESERVED_15_6__SHIFT                                          0x6
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__ACK_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_VAL__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RX_VALID_OVRD_EN__SHIFT                                 0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__ADAPT_ACK__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_ACK__RESERVED_15_1__SHIFT                                     0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__ADAPT_FOM__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_ADAPT_FOM__RESERVED_15_8__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__TXPRE_DIR__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPRE_DIR__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__TXMAIN_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXMAIN_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__TXPOST_DIR__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_TXPOST_DIR__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_CLK_EN_RST__SHIFT                                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RX_DIV16P5_CLK_EN_RST__SHIFT                            0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_CLK_CTRL_0__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_FW_XF_OUT_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_REQ_IRQ_MSK__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RATE_IRQ_MSK__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_PSTATE_IRQ_MSK__SHIFT                                0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_REQ_IRQ_MSK__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_ADAPT_DIS_IRQ_MSK__SHIFT                             0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_RESET_IRQ_MSK__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_TERM_CTRL_IRQ_MSK__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_GLB_IRQ_MSK__SHIFT                            0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_IQ_START_IRQ_MSK__SHIFT                       0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_VDAC_START_IRQ_MSK__SHIFT                     0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_ERROR_CLEAR_IRQ_MSK__SHIFT                    0xa
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_INIT_IRQ_MSK__SHIFT                           0xb
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RX_MARGIN_FINISH_IRQ_MSK__SHIFT                         0xc
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_MASK__RESERVED_15_13__SHIFT                                   0xd
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_RATE_IRQ_EN__SHIFT                               0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_REQ_IRQ_BLOCK_ACK_EN__SHIFT                      0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_TERM_CTRL_IRQ_EN__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_GLB_IRQ_EN__SHIFT                         0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_IQ_START_IRQ_EN__SHIFT                    0x5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_VDAC_START_IRQ_EN__SHIFT                  0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_ERROR_CLEAR_IRQ_EN__SHIFT                 0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_INIT_IRQ_EN__SHIFT                        0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RX_MARGIN_FINISH_IRQ_EN__SHIFT                      0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_IRQ_EN_FLAGS__RESERVED_15_10__SHIFT                               0xa
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RX_RESET__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RX_REQ__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RX_RATE_IRQ__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RX_PSTATE_IRQ__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RX_ADAPT_REQ_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RX_ADAPT_DIS_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RX_RESET_IRQ_CLR__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RESET_IRQ_CLR__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RX_REQ_IRQ_CLR__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RX_RATE_IRQ_CLR__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_RATE_IRQ_CLR__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RX_PSTATE_IRQ_CLR__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_PSTATE_IRQ_CLR__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RX_ADAPT_REQ_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RX_ADAPT_DIS_IRQ_CLR__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RX_TERM_CTRL_IRQ__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RX_TERM_CTRL_CLR__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_TERM_CTRL_IRQ_CLR__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RX_MARGIN_IQ_START_IRQ__SHIFT             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RX_MARGIN_IQ_START_IRQ_CLR__SHIFT     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_IQ_START_IRQ_CLR__RESERVED_15_1__SHIFT                  0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RX_MARGIN_VDAC_START_IRQ__SHIFT         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RX_MARGIN_VDAC_START_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_VDAC_START_IRQ_CLR__RESERVED_15_1__SHIFT                0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RX_MARGIN_ERROR_CLEAR_IRQ__SHIFT       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RX_MARGIN_ERROR_CLEAR_IRQ_CLR__SHIFT  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_ERROR_CLEAR_IRQ_CLR__RESERVED_15_1__SHIFT               0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RX_MARGIN_INIT_IRQ__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RX_MARGIN_INIT_IRQ_CLR__SHIFT             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_INIT_IRQ_CLR__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RX_MARGIN_FINISH_IRQ__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RX_MARGIN_FINISH_IRQ_CLR__SHIFT         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_FINISH_IRQ_CLR__RESERVED_15_1__SHIFT                    0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RX_MARGIN_GLB_IRQ__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RX_MARGIN_GLB_IRQ_CLR__SHIFT               0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_IRQ_CTL_RX_MARGIN_GLB_IRQ_CLR__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RX_TERM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_TERM_CODE__RESERVED_15_6__SHIFT                                       0x6
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__ENABLE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_OFFCAN_CONT_STATUS__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__ENABLE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_CONT_STATUS__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__ADAPT_MODE__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE__RESERVED_15_2__SHIFT                                      0x2
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RX_ADAPT_SEL__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_SEL__RESERVED_15_1__SHIFT                                       0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RX_PPM_DRIFT_VLD__SHIFT                                    0xe
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PPM_DRIFT__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__CDR_DET_STATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_CDR_DET_STATUS__RESERVED_15_3__SHIFT                                  0x3
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_CDR_TRACK_EN__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RX_DFE_TAP1_ADAPT_OVRD_EN__SHIFT                        0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_DELTA_IQ__SHIFT                                 0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__DISABLE_MARGIN_IQ_SCALE__SHIFT                          0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PMA_MISC_CTL__RESERVED_15_4__SHIFT                                    0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_0_OVRD_EN__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_1_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_2_OVRD_EN__SHIFT                    0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RX_ADAPT_MODE_3_OVRD_EN__SHIFT                    0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_OVRD_EN__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RX_ADAPT_MODE_EN__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MODE_EN__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RX_ADAPT_MM_FOM__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_MM_FOM__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RX_ADAPT_STARTUP_FOM__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADAPT_STARTUP_FOM__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RX_ADPT_REF_ERR_EVEN__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_EVEN__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RX_ADPT_REF_ERR_ODD__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_ADPT_REF_ERR_ODD__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RX_ADPT_IQ_LEFT__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_LEFT__RESERVED_15_7__SHIFT                                 0x7
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RX_ADPT_IQ_RIGHT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_ADPT_IQ_RIGHT__RESERVED_15_7__SHIFT                                0x7
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RX_PHSADJ_LIN__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RX_PHSADJ_MAP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__VAL__SHIFT                                         0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_MAP_UPDATE__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_MARGIN_IQ_DELTA__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__VAL__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_VDAC_DELTA__RESERVED_15_10__SHIFT                           0xa
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__BYPASS_ADJUST_LIN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_STATUS__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RX_MARGIN_ERROR__RESERVED_15_6__SHIFT                                 0x6
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_RATE_IRQ_EN__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_WIDTH_IRQ_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_VCO_FREQ_IRQ_EN__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_MISC_IRQ_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_TERM_CTRL_IRQ_EN__SHIFT                              0x4
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_CTRL_IRQ_EN__SHIFT                               0x5
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DCC_BYP_IRQ_EN__SHIFT                                0x6
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_DFE_BYP_IRQ_EN__SHIFT                                0x7
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_LANE_EQ_IRQ_EN__SHIFT                                     0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RX_CAL_DONE_IRQ_EN__SHIFT                                    0x9
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_FSM_CTL__RESERVED_15_10__SHIFT                                        0xa
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RX_RATE_IRQ_ACK__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_RATE_IRQ_ACK__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_WR__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__IS_OVERLAP_CODE__SHIFT                               0x8
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_RD__RESERVED_15_9__SHIFT                                 0x9
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__VAL__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_STEP_CODE_WR__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__VAL__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_IQ_LIN_CODE_RD__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__PHSADJ_LIN_UPDATE_EN__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_CTL_PHSADJ_LIN_UPDATE_EN__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_REQ_OVRD_EN__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RX_RESET_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_OUT_0__RESERVED_15_4__SHIFT                                   0x4
//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__ACK__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_IN_0__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_VAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RX_ACK_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEX_DIG_RX_PMA_XF_OVRD_IN_0__RESERVED_15_2__SHIFT                                    0x2
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_ADDR__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_JMP_EN__SHIFT                                          0xc
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_CMD_START__SHIFT                                       0xd
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__FSM_OVRD_EN__SHIFT                                         0xe
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_OVRD_CTL__RESERVED_15_15__SHIFT                                      0xf
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__BANK__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_JMP_BANK__RESERVED_15_3__SHIFT                                       0x3
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__ENABLE_CREG_MASK_AUTO_RST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FSM_CTL_0__RESERVED_15_1__SHIFT                                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_0__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_ADDR__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__BREAKPOINT_EN__SHIFT                                   0xe
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_BREAKPOINT_1__RESERVED_15_15__SHIFT                                  0xf
//C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_MEM_ADDR_MON__MEM_ADDR__SHIFT                                            0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__STATE__SHIFT                                                 0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__CMD_RDY__SHIFT                                               0x5
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_OVFLW__SHIFT                                             0x6
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__ALU_RES_EQ0__SHIFT                                           0x7
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WAIT_CNT_EQ0__SHIFT                                          0x8
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__WRMSK_DISABLED__SHIFT                                        0x9
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RDMSK_DISABLED__SHIFT                                        0xa
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_STATUS_MON__RESERVED_15_11__SHIFT                                        0xb
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__INT_CFG_DONE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__CMN_CAL_DONE__SHIFT                                        0x1
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_CFG_STAGE__RESERVED_15_2__SHIFT                                       0x2
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_SCRATCH_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_REG_LOCK__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__CR_MEM_LOCK__SHIFT                                              0x1
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_CR_LOCK__RESERVED_15_2__SHIFT                                            0x2
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_0__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_1
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_1__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_2
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_2__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_3
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FW_DEBUG_3__VAL__SHIFT                                                   0x0
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__FAST_SUP__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_SUP__RESERVED_15_1__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__FAST_TX_CMN_MODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_CMN_MODE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__FAST_TX_RXDET__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_RXDET__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__SKIP_TX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__SKIP_TX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__SKIP_TX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__FAST_TX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__FAST_TX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_TX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__SKIP_TX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__SKIP_TX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_TX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__FAST_RX_STARTUP_CAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_STARTUP_CAL__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__FAST_RX_ADAPT__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_ADAPT__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__FAST_RX_PWRUP__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_PWRUP__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__FAST_RX_VCO_WAIT__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_WAIT__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__FAST_RX_VCO_CAL__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_VCO_CAL__RESERVED_15_1__SHIFT                                    0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__FAST_RX_CONT_CAL_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_CAL_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__FAST_RX_CONT_ADAPT__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_FAST_RX_CONT_ADAPT__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__SKIP_RX_AFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__SKIP_RX_DFE_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__SKIP_RX_DFE_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_DELTA_STARTUP__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__SKIP_RX_IQ_STARTUP_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__SKIP_RX_AFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__SKIP_RX_DFE_STARTUP_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__SKIP_RX_IQ_STARTUP_ADAPT__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQ_STARTUP_ADAPT__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__SKIP_RX_CONT_PHASE_CAL__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CONT_PHASE_CAL__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__SKIP_RX_AFE_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_AFE_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__SKIP_RX_REFLVL_CONT_ADAPT__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_REFLVL_CONT_ADAPT__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__SKIP_RX_VGA_CONT_ADAPT__SHIFT                    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_CONT_ADAPT__RESERVED_15_1__SHIFT                             0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__SKIP_RX_PHS_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__SKIP_RX_PHS_EXT_STARTUP_CAL__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_PHS_EXT_STARTUP_CAL__RESERVED_15_1__SHIFT                        0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__SKIP_RX_DCC_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__SKIP_RX_DCC_CONT_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_CONT_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__SKIP_RX_DCC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__SKIP_SIGDET_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_SIGDET_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__SKIP_VGEN_STARTUP_CAL__SHIFT                      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_VGEN_STARTUP_CAL__RESERVED_15_1__SHIFT                              0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__SKIP_RX_IQC_RATE_CAL__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_IQC_RATE_CAL__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__SKIP_RX_DCC_DATA_STARTUP_CAL__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_DATA_STARTUP_CAL__RESERVED_15_1__SHIFT                       0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__SKIP_RX_DCC_BYPASS_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__SKIP_RX_DCC_PHASE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_PHASE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__SKIP_RX_HALF_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_HALF_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__SKIP_RX_FULL_RATE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_FULL_RATE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__SKIP_RX_ERROR_STARTUP_CAL__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ERROR_STARTUP_CAL__RESERVED_15_1__SHIFT                          0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__SKIP_RX_BYPASS_STARTUP_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BYPASS_STARTUP_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__SKIP_RX_VGA_SLICER_STARTUP_CAL__SHIFT    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_SLICER_STARTUP_CAL__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__SKIP_RX_BUF_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_BUF_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__SKIP_RX_ADAPT_RELOAD__SHIFT                        0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ADAPT_RELOAD__RESERVED_15_1__SHIFT                               0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SKIP_RX_DFE_COARSE_STARTUP_ADAPT__SHIFT  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_COARSE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                   0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__SKIP_RX_DFE_FINE_STARTUP_ADAPT__SHIFT    0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DFE_FINE_STARTUP_ADAPT__RESERVED_15_1__SHIFT                     0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__SKIP_RX_DCC_RANGE_RATE_CAL__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_RATE_CAL__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__SKIP_RX_DCC_RANGE_STARTUP_CAL__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_DCC_RANGE_STARTUP_CAL__RESERVED_15_1__SHIFT                      0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__SKIP_RX_VGA_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_VGA_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__SKIP_RX_CTLE_STARTUP_CAL__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_CTLE_STARTUP_CAL__RESERVED_15_1__SHIFT                           0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__SKIP_RX_ATT_STARTUP_CAL__SHIFT                  0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_ATT_STARTUP_CAL__RESERVED_15_1__SHIFT                            0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__SKIP_RX_MARGINING__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_SKIP_RX_MARGINING__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RST_CAL_DONE__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEX_DIG_FSM_RX_CAL_STATUS__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RX_ERR_SLICER_STATE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_0__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_1__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__SPARE_STATE_2__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_0__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_0__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_1__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_2__SHIFT                                      0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__SPARE_STATE_3__SHIFT                                      0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FW_STATES_1__RESERVED_15_4__SHIFT                                      0x4
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_ADDR__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__BREAKPOINT_EN__SHIFT                                 0xe
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MEM_BREAKPOINT_2__RESERVED_15_15__SHIFT                                0xf
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_INIT_DONE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_MODE__SHIFT                                         0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__REC_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_CTRL__RESERVED_15_3__SHIFT                                    0x3
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__SRAM_REC_MAX_ITER__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_MAX_ITER__RESERVED_15_5__SHIFT                                0x5
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_BASE_ADDR__SRAM_REC_BASE_ADDR__SHIFT                          0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ADDR__SRAM_REC_ADDR__SHIFT                                    0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__SRAM_REC_ITER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_ITER__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__REC_EN__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_SRAM_REC_EN__RESERVED_15_1__SHIFT                                      0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_START_LOOP_CNT__VAL__SHIFT                                         0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CCA_WAIT_CNT__VAL__SHIFT                                               0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_STARTUP__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_STARTUP__SHIFT               0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_CAL_RATE__SHIFT                        0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__SKIP_TX_DCC_RANGE_CAL_RATE__SHIFT                  0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_STARTUP_ALGO_CTL_0__RESERVED_15_4__SHIFT                               0x4
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__SKIP_TX_DCC_CAL_CONT__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CONT_ALGO_CTL_0__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_SUP__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_CMN_MODE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_RXDET__SHIFT                                     0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_STARTUP_CAL__SHIFT                               0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__FAST_TX_PWRUP__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_FAST_FLAGS_0__RESERVED_15_5__SHIFT                                     0x5
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__TX_HP_PROT_EN_OVRD_EN__SHIFT                    0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_OVRD_IN__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__TX_HP_PROT_EN__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_TX_HP_PROT_EN_IN__RESERVED_15_1__SHIFT                                 0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__LANE_XCVR_MODE_OVRD_EN__SHIFT                  0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_OVRD_IN__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__LANE_XCVR_MODE__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_LANE_XCVR_MODE_IN__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__INIT_PWRUP_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_INIT_PWRUP_DONE__RESERVED_15_1__SHIFT                                  0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE__SHIFT                                              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__DISABLE_OVRD_EN__SHIFT                                      0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_OVRD_IN_0__RESERVED_15_2__SHIFT                                        0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_FULL_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_DCC_HALF_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                            0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                            0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLA_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE__RESERVED_15_1__SHIFT                                   0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__TX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_CM_CODE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CODE__TX_DCC_DIFF_CODE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__HALF_RATE__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_DIFF_CODE__FULL_RATE__SHIFT                                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__HALF_RATE__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_DCC_CM_CODE__FULL_RATE__SHIFT                                          0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__TX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__TX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_TX_IN_0__RESERVED_15_1__SHIFT                                             0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_AFE_CAL_STARTUP__SHIFT                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_REF_CAL_EXT_STARTUP__SHIFT             0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ATT_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_VGA_CAL_EXT_STARTUP__SHIFT             0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_CTLE_CAL_STARTUP__SHIFT                0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_CAL_STARTUP__SHIFT                  0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_IQ_DELTA_STARTUP__SHIFT                0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_STARTUP__SHIFT                 0x9
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_PHS_CAL_EXT_STARTUP__SHIFT             0xa
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_STARTUP__SHIFT                 0xb
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_DFE_CAL_EXT_STARTUP__SHIFT             0xc
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_ERROR_CAL_STARTUP__SHIFT               0xd
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__SKIP_RX_BYPASS_CAL_STARTUP__SHIFT              0xe
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_0__RESERVED_15_15__SHIFT                          0xf
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_VGEN_CAL_STARTUP__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_SIGDET_CAL_STARTUP__SHIFT                 0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_VGA_SLICER_CAL_STARTUP__SHIFT          0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_BUF_CAL_STARTUP__SHIFT                 0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_STARTUP__SHIFT                 0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_STARTUP__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_FULL_RATE_CAL_STARTUP__SHIFT           0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_HALF_RATE_CAL_STARTUP__SHIFT           0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_DATA_CAL_STARTUP__SHIFT            0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_PHASE_CAL_STARTUP__SHIFT           0x9
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_BYPASS_CAL_STARTUP__SHIFT          0xa
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_CAL_RATE__SHIFT                    0xb
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_DCC_RANGE_CAL_RATE__SHIFT              0xc
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__SKIP_RX_IQC_CAL_RATE__SHIFT                    0xd
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_CAL_ALGO_CTL_1__RESERVED_15_14__SHIFT                          0xe
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_0_STARTUP__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_0_STARTUP__SHIFT      0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_0_STARTUP__SHIFT  0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_0_STARTUP__SHIFT  0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_0_STARTUP__SHIFT       0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_AFE_ADAPT_BANK_1_STARTUP__SHIFT      0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_ADAPT_BANK_1_STARTUP__SHIFT      0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_COARSE_ADAPT_BANK_1_STARTUP__SHIFT  0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_DFE_FINE_ADAPT_BANK_1_STARTUP__SHIFT  0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_IQ_ADAPT_BANK_1_STARTUP__SHIFT       0x9
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_ADAPT_RELOAD__SHIFT                  0xa
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_TX_INC_DEC_STARTUP__SHIFT            0xb
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_FOM_STARTUP__SHIFT                   0xc
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__SKIP_RX_MARGINING__SHIFT                     0xd
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_STARTUP_ADAPT_ALGO_CTL_0__RESERVED_15_14__SHIFT                        0xe
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_AFE_CAL_CONT__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_PHS_CAL_CONT__SHIFT                             0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_CAL_CONT__SHIFT                             0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DCC_CAL_CONT__SHIFT                             0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_REFLVL_ADAPT_CONT__SHIFT                        0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_VGA_ADAPT_CONT__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP1_CONT__SHIFT                      0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_DFE_ADAPT_TAP25_CONT__SHIFT                     0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__SKIP_RX_FOM_CONT__SHIFT                                 0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CONT_ALGO_CTL__RESERVED_15_9__SHIFT                                    0x9
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_STARTUP_CAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_ADAPT__SHIFT                                       0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_CAL_ADAPT__SHIFT                              0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_CONT_ADAPT__SHIFT                                  0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_PWRUP__SHIFT                                       0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_CAL__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__FAST_RX_VCO_WAIT__SHIFT                                    0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_FAST_FLAGS__RESERVED_15_7__SHIFT                                       0x7
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_OFST__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__VGEN_VDAC_DONE__SHIFT                                  0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VGEN_VDAC_OFST__RESERVED_15_9__SHIFT                                   0x9
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_LF_CAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RX_SIGDET_HF_CAL__SHIFT                                    0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_CAL__RESERVED_15_13__SHIFT                                      0xd
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__AFE_RTRIM__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_RTRIM__RESERVED_15_1__SHIFT                                        0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__REF_VDAC_OFST__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_VDAC_OFST__RESERVED_15_8__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__REF_EXT_VDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EXT_VDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__REF_EE_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EE_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__REF_EO_VDAC_OFST__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_REF_EO_VDAC_OFST__RESERVED_15_8__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EE_VDAC_OFST__DFE_EEL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOH_VDAC_OFST__SHIFT                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EO_VDAC_OFST__DFE_EOL_VDAC_OFST__SHIFT                             0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__SETUP_REF_CTLE_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_CTLE_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__SETUP_REF_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_REF_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__SETUP_SLC_VGA1_IDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SETUP_SLC_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__VAL__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_VDAC_RANGE_SEL__RESERVED_15_2__SHIFT                                   0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__AFE_ATT_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_ATT_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_0__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_1__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_2__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__AFE_CTLE_IDAC_OFST__SHIFT                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_CTLE_IDAC_OFST_BANK_3__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__AFE_VGA1_IDAC_OFST__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_VGA1_IDAC_OFST__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__AFE_BUF_IDAC_OFST__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_AFE_BUF_IDAC_OFST__RESERVED_15_8__SHIFT                                0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__DFE_PHASE_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__DFE_PHASE_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__DFE_PHASE_EVEN_LOW_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__DFE_PHASE_ODD_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_PHASE_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__DFE_DATA_EVEN_HIGH_VDAC_OFST__SHIFT      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                     0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__DFE_DATA_EVEN_LOW_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_EVEN_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__DFE_DATA_ODD_HIGH_VDAC_OFST__SHIFT        0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_HIGH_VDAC_OFST__RESERVED_15_8__SHIFT                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__DFE_DATA_ODD_LOW_VDAC_OFST__SHIFT          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DATA_ODD_LOW_VDAC_OFST__RESERVED_15_8__SHIFT                       0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__DFE_BYPASS_EVEN_VDAC_OFST__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__DFE_BYPASS_ODD_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_BYPASS_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__DFE_ERROR_EVEN_VDAC_OFST__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_EVEN_VDAC_OFST__RESERVED_15_8__SHIFT                         0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__DFE_ERROR_ODD_VDAC_OFST__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_ERROR_ODD_VDAC_OFST__RESERVED_15_8__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__IQ_CAL_DIVN__SHIFT                                        0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_DIVN__RESERVED_15_8__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MAX__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__HALF_RATE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_MIN__FULL_RATE__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__BYPASS__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_RESET__DATA__SHIFT                                              0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__BYPASS_FULL_RATE__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_IQ_ADJUST__DATA_FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_0__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_0__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_0__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_0__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_0__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_0__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_1__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_1__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_1__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_1__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_1__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_1__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_2__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_2__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_2__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_2__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_2__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_2__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__FULL_VAL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__HALF_VAL__SHIFT                                 0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_BANK_3__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_FULL_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__CM_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_DATA_BANK_3__DIFF_VAL__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__CM_VAL__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_BYP_BANK_3__DIFF_VAL__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__CM_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_HALF_PHASE_BANK_3__DIFF_VAL__SHIFT                                 0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__HALF_RATE_VAL__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL_BANK_3__FULL_RATE_VAL__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_FULL_DONE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__CAL_HALF_DONE__SHIFT                                  0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE_BANK_3__RESERVED_15_2__SHIFT                                  0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RX_RECAL_BANK_SEL__SHIFT                                 0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_BANK_SEL__RESERVED_15_2__SHIFT                                     0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RX_DCC_CTRL_RANGE__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_CTRL_RANGE_CODE__RESERVED_15_4__SHIFT                              0x4
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_CM_CODE__SHIFT                              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CODE__RX_DCC_DATA_DIFF_CODE__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_CM_CODE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CODE__RX_DCC_BYP_DIFF_CODE__SHIFT                              0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_CM_CODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CODE__RX_DCC_PHASE_DIFF_CODE__SHIFT                          0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__HALF_RATE__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_DIFF_CODE__FULL_RATE__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__HALF_RATE__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_DATA_CM_CODE__FULL_RATE__SHIFT                                     0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_DIFF_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__HALF_RATE__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_BYP_CM_CODE__FULL_RATE__SHIFT                                      0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__HALF_RATE__SHIFT                                  0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_DIFF_CODE__FULL_RATE__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__HALF_RATE__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DCC_PHASE_CM_CODE__FULL_RATE__SHIFT                                    0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__VAL__SHIFT                                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CAL__RESERVED_15_8__SHIFT                                           0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__VAL__SHIFT                                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CAL_DONE__RESERVED_15_1__SHIFT                                         0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_OFST__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__IQ_ADPT_SWEEP_LVL__SHIFT                                     0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_0__RESERVED_15_7__SHIFT                                         0x7
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH_CENTER__SHIFT                                    0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_CTL_1__DPLL_THRESH__SHIFT                                           0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__LEFT_LIMIT__SHIFT                                       0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RIGHT_LIMIT__SHIFT                                      0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_LIMIT__RESERVED_15_10__SHIFT                                   0xa
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__ADPT_ERR_SLC_MODE__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ERR_SLC_MODE__RESERVED_15_2__SHIFT                                0x2
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_0__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_0__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_0__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_0__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_0__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_0__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_0__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_0__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_0__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_0__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__ATT_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_ATT_BANK_1__RESERVED_15_8__SHIFT                                  0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__VGA_ADPT_VAL__SHIFT                                   0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_VGA_BANK_1__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_BOOST_ADPT_VAL__SHIFT                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__CTLE_POLE_ADPT_VAL__SHIFT                            0xa
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTLE_BANK_1__RESERVED_15_12__SHIFT                                0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__DFE_TAP1_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP1_BANK_1__RESERVED_15_13__SHIFT                            0xd
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__DFE_TAP2_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP2_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__DFE_TAP3_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP3_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__DFE_TAP4_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP4_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__DFE_TAP5_ADPT_VAL__SHIFT                         0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_DFE_TAP5_BANK_1__RESERVED_15_12__SHIFT                            0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__DFE_DEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__DFE_DEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__DFE_DOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__DFE_DOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_DOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__DFE_EEH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__DFE_EEL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EEL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__DFE_EOH_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOH_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__DFE_EOL_TAP1_OFST__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_EOL_TAP1_OFST_BANK_1__RESERVED_15_6__SHIFT                         0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__DFE_TAP1_OFST_VLD__SHIFT                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_DFE_TAP1_OFST_VLD_BANK_1__RESERVED_15_1__SHIFT                         0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ__SHIFT                                      0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RX_ADPT_IQ_VLD__SHIFT                                  0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_IQ_BANK_1__RESERVED_15_8__SHIFT                                   0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_EVEN__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_REF_ERR_BANK_1__RX_ADPT_REF_ERR_ODD__SHIFT                        0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RX_ADAPT_DONE__SHIFT                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADAPT_DONE_BANK_1__RESERVED_15_1__SHIFT                                0x1
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXMAIN_DIR_INV__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPRE_DIR_INV__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__TXPOST_DIR_INV__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_EQ_DIR_POLARITY_CTL__RESERVED_15_3__SHIFT                           0x3
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_OFF_MULT__SHIFT                                     0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__TX_PRE_THRESH_DIV__SHIFT                                   0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_PRE_DIV__RESERVED_15_9__SHIFT                                       0x9
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__TX_MAIN_ATT_HIGH_THRESHOLD__SHIFT               0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_ATT_THRESHOLD__RESERVED_15_6__SHIFT                            0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_LOW_THRESHOLD__SHIFT                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__TX_MAIN_VGA_HIGH_THRESHOLD__SHIFT               0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_MAIN_VGA_THRESHOLD__RESERVED_15_8__SHIFT                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_LOW_THRESHOLD__SHIFT            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__TX_POST_BOOST_HIGH_THRESHOLD__SHIFT           0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_BOOST_THRESHOLD__RESERVED_15_10__SHIFT                         0xa
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_LOW_THRESHOLD__SHIFT              0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_TX_POST_TAP1_THRESHOLD__TX_POST_TAP1_HIGH_THRESHOLD__SHIFT             0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_0__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_1__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_2__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_3__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_4__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_5__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_6__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_7__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_8__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_9__VAL__SHIFT                                                 0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_10__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_11__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_12__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_13__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_14__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_15__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_16__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_17__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_18__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_19__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_20__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_21__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_22__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_23__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_24__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_25__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_26__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_27__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_ADPT_CTL_28__VAL__SHIFT                                                0x0
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MIN__SHIFT                                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IQ_MARGIN_RANGE__MAX__SHIFT                                            0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_DETECTOR_EN__SHIFT                            0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RX_CDR_PPM_MONITOR_MODE__SHIFT                       0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__DIS_IN_ADAPT__SHIFT                                  0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_DETECTOR_CTL__RESERVED_15_3__SHIFT                                 0x3
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__VAL__SHIFT                                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_CDR_RECOVERY_TIME__RESERVED_15_12__SHIFT                               0xc
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE__SHIFT                                           0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_DISABLE_OVRD_EN__SHIFT                                   0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN__SHIFT                                           0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_EN_OVRD_EN__SHIFT                                   0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC__SHIFT                                         0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_TERM_ACDC_OVRD_EN__SHIFT                                 0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_VAL__SHIFT                             0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_LF_EN_OVRD_EN__SHIFT                              0x7
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_VAL__SHIFT                             0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_EN_OVRD_EN__SHIFT                              0x9
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_VAL__SHIFT                       0xa
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_SIGDET_HF_FILT_DIS_OVRD_EN__SHIFT                        0xb
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_VAL__SHIFT                           0xc
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RX_VREFGEN_MASTER_OVRD_EN__SHIFT                            0xd
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_IN_0__RESERVED_15_14__SHIFT                                       0xe
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RX_SIGDET_EN_MASK_CNT__SHIFT                       0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_EN_MASK_CTL__RESERVED_15_8__SHIFT                               0x8
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_FILT_CNT__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_HF_FILT_CNT__SHIFT                          0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RX_SIGDET_LF_HOLD__SHIFT                              0x8
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_SIGDET_FILT_CTL__RESERVED_15_9__SHIFT                                  0x9
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_VAL__SHIFT                               0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_LF_OVRD_EN__SHIFT                                0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_VAL__SHIFT                               0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RX_SIGDET_HF_OVRD_EN__SHIFT                                0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OVRD_OUT_0__RESERVED_15_4__SHIFT                                       0x4
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_VAL__SHIFT                          0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_GD_EN_OVRD_EN__SHIFT                           0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_VAL__SHIFT                          0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_TERM_DC_EN_OVRD_EN__SHIFT                           0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_VAL__SHIFT                          0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RX_VREFGEN_EN_OVRD_EN__SHIFT                           0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_PMA_OVRD_OUT_0__RESERVED_15_6__SHIFT                                   0x6
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_DISABLE__SHIFT                                                0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_EN__SHIFT                                                0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_TERM_ACDC__SHIFT                                              0x2
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_LF_EN__SHIFT                                           0x3
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_EN__SHIFT                                           0x4
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_SIGDET_HF_FILT_DIS__SHIFT                                     0x5
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RX_VREFGEN_MASTER__SHIFT                                         0x6
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_IN_0__RESERVED_15_7__SHIFT                                             0x7
//C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_LF__SHIFT                                             0x0
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RX_SIGDET_HF__SHIFT                                             0x1
#define C20_PHY_CR1_RAWLANEAONX_DIG_RX_OUT_0__RESERVED_15_2__SHIFT                                            0x2


// addressBlock: c20_phy_lane0_pipe1_rdpcspipemsgbusind
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS__DEBUG_INFO_ADDRESS__SHIFT               0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE__DEBUG_INFO_VALUE__SHIFT                   0x0
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
//C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
#define C20_PHY_LANE0_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2


// addressBlock: c20_phy_lane1_pipe1_rdpcspipemsgbusind
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__START_MARGIN__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__MARGIN_VOLTAGE_OR_TIMING__SHIFT         0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ERROR_COUNT_RESET__SHIFT                0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__SAMPLE_COUNT_RESET__SHIFT               0x3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__ENABLE_DESTR_MARGINING__SHIFT           0x4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL0__RESERVED__SHIFT                         0x5
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_OFFSET__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_MARGIN_CONTROL1__MARGIN_DIRECTION__SHIFT                 0x7
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_ELASTIC_BUFFER_CONTROL__ELASTIC_BUFFER_DEPTH_CONTROL__SHIFT  0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__ELASTIC_BUFFER_MODE__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RX_POLARITY__SHIFT                             0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL0__RESERVED__SHIFT                                0x2
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RX_EQ_TRAINING__SHIFT                          0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__IO_RECAL__SHIFT                                0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL1__RESERVED__SHIFT                                0x2
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_VAL__SHIFT                               0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RX_EQ_IN_PROGRESS__SHIFT                       0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__INVALID_REQUEST__SHIFT                         0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL3__RESERVED__SHIFT                                0x3
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__BLOCK_ALIGN_CONTROL__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__ELASTIC_BUFFER_RESET_CONTROL__SHIFT            0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_RX_CONTROL4__RESERVED__SHIFT                                0x2
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                           0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                       0x6
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL2__RESERVED__SHIFT                                0x7
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                          0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL3__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL4__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT                  0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__RESERVED__SHIFT                                0x6
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT           0x7
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__FS_5_0__SHIFT                                  0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL6__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__LF_5_0__SHIFT                                  0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL7__RESERVED__SHIFT                                0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_MARGIN__SHIFT                               0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__TX_SWING__SHIFT                                0x3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_TX_CONTROL8__RESERVED__SHIFT                                0x4
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__TX_DEEMPH_5_0__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__DISABLE_SINGLE_TX__SHIFT                   0x6
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL2__RESERVED__SHIFT                            0x7
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__TX_DEEMPH_11_6__SHIFT                      0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL3__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__TX_DEEMPH_17_12__SHIFT                     0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL4__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__LOCAL_PRESET_INDEX_5_0__SHIFT              0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__RESERVED__SHIFT                            0x6
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL5__GET_LOCAL_PRESET_COEFFICIENTS__SHIFT       0x7
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_MARGIN__SHIFT                           0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__TX_SWING__SHIFT                            0x3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_TX_CONTROL8__RESERVED__SHIFT                            0x4
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__ENCODE_DECODE_BYPASS__SHIFT                0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_COMMON_CONTROL0__RESERVED__SHIFT                            0x1
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_L__WR_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_ADDRESS_H__WR_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_L__WR_DATA_L__SHIFT                         0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_WR_DATA_H__WR_DATA_H__SHIFT                         0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_L__RD_ADDRESS_L__SHIFT                   0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_ADDRESS_H__RD_ADDRESS_H__SHIFT                   0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_L__RD_DATA_L__SHIFT                         0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RD_DATA_H__RD_DATA_H__SHIFT                         0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__CONTEXT_TOGGLE__SHIFT           0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__DP_RATE_IN_CUSTOM_SERDES__SHIFT  0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__PIXEL_CLK_GATE__SHIFT           0x5
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_DP__SHIFT                    0x6
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_CUSTOM_SERDES_RATE__IS_FRL__SHIFT                   0x7
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__HDMI_RATE__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_HDMI_RATE__RESERVED__SHIFT                          0x2
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__CUSTOM_WIDTH__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_CUSTOM_WIDTH__RESERVED__SHIFT                           0x2
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_LFPS_CTRL__LFPS_ELECIDLE_TIMER__SHIFT               0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_ADDRESS__DEBUG_INFO_ADDRESS__SHIFT               0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_DEBUG_INFO_VALUE__DEBUG_INFO_VALUE__SHIFT                   0x0
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_HDP_EQ_OVRD_G1__SHIFT                          0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G2__SHIFT                              0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__TX_EQ_OVRD_G1__SHIFT                              0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_OVRD__RESERVED__SHIFT                                   0x3
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__TX_EQ_PRE_G1__SHIFT                           0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD__RESERVED__SHIFT                               0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__TX_EQ_MAIN_G1__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__TX_EQ_POST_G1__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD__RESERVED__SHIFT                              0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__TX_EQ_PRE_G2__SHIFT                         0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_PRE_OVRD_2__RESERVED__SHIFT                             0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__TX_EQ_MAIN_G2__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_MAIN_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__TX_EQ_POST_G2__SHIFT                       0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_VDR_POST_OVRD_2__RESERVED__SHIFT                            0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__TX_HDP_EQ_PRE__SHIFT                      0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_PRE_OVRD__RESERVED__SHIFT                           0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__TX_HDP_EQ_MAIN__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_MAIN_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__TX_HDP_EQ_POST__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_HDP_VDR_POST_OVRD__RESERVED__SHIFT                          0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLA_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__MPLLB_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RX_CALIBRATIONS_BANK_OVRD_VAL__SHIFT  0x4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_BANK_SEL__RESERVED__SHIFT                     0x6
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLA_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__MPLLB_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX1_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__TX2_RECAL_FORCE_EN_OVRD_VAL__SHIFT  0x3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RX_RECAL_FORCE_EN_OVRD_VAL__SHIFT   0x4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_FORCE_EN__RESERVED__SHIFT                     0x5
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLA_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__MPLLB_RECAL_SKIP_EN_OVRD_VAL__SHIFT  0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX1_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__TX2_RECAL_SKIP_EN_OVRD_VAL__SHIFT    0x3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RX_RECAL_SKIP_EN_OVRD_VAL__SHIFT     0x4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_SKIP_EN__RESERVED__SHIFT                      0x5
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_L2L_DESKEW_EN_OVRD_VAL__SHIFT        0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX1_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x2
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__TX2_CLK_DESKEW_EN_OVRD_VAL__SHIFT        0x3
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__DESKEW_EN_3P6_NS__SHIFT                  0x4
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_DESKEW_EN__RESERVED__SHIFT                          0x5
//C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RECAL_OVRD_EN__SHIFT                    0x0
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__DESKEW_OVRD_EN__SHIFT                   0x1
#define C20_PHY_LANE1_PIPE1_UPCSLANE_PIPE_LPC_PHY_C20_VDR_RECAL_OVRD__RESERVED__SHIFT                         0x2


#endif